公开(公告)号：US20190266928A1

公开(公告)日：2019-08-29

申请号：US16139419

申请日：2018-09-24

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Il-Joo KIM ,  Sang-Uk LIM

IPC: G09F9/33 ,  G09G3/32 ,  G09G3/20 ,  H01L25/075

Abstract: A display device includes: a first pixel including a first light emitting diode (LED) and a first capacitor including a first electrode connected to a first power source voltage providing a driving voltage to an anode of the first light emitting diode (LED) or to an initialization voltage, and a second electrode connected to the anode of the first light emitting diode (LED); and a second pixel including a second light emitting diode (LED) and a second capacitor including a first electrode connected to the first power source voltage providing the driving voltage to an anode of the second light emitting diode (LED) or to an initialization voltage, and a second electrode connected to the anode of the second light emitting diode (LED), wherein capacitance of the second capacitor is less than capacitance of the first capacitor.

公开(公告)号：US20190189053A1

公开(公告)日：2019-06-20

申请号：US16134923

申请日：2018-09-18

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Ji Hye LEE

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2320/0214 ,  G09G2320/0238 ,  G09G2320/0247

Abstract: A pixel includes an organic light-emitting diode (OLED), a storage capacitor, and first to fourth transistors. The first transistor includes a gate electrode (GE), a first electrode (FE), and a second electrode (SE), and is configured to control, in response to a voltage of a first node (FN) coupled to the GE, current supplied from a first power source (PS) coupled to the FE to a second PS via the OLED. The storage capacitor is coupled between the FN and the first PS. The second transistor is coupled between a data line and the first transistor. The third transistor includes a FE coupled to the FN and a SE coupled to the SE of the first transistor. The fourth transistor includes a FE coupled to the FN and a SE coupled to the SE of the first transistor, and is configured to transmit an initialization voltage to the FN.