公开(公告)号：US20240095532A1

公开(公告)日：2024-03-21

申请号：US18522982

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsun PARK ,  Yoojin KIM ,  Hyeongseok YU ,  Sehwan LEE ,  Junwoo JANG

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: A method of processing data includes identifying a sparsity among information, included in input data, based on valid information or invalid information included in the input data, rearranging the input data based on the sparsity among the information indicating a distribution of the invalid values included in the input data, and generating, by performing an operation on the rearranged input data in the neural network, an output data.

公开(公告)号：US20230394277A1

公开(公告)日：2023-12-07

申请号：US18453615

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan LEE

IPC: G06N3/04 ,  G06F17/15 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06F17/15 ,  G06N3/045

Abstract: Provided are a method of performing a convolution operation between a kernel and an input feature map based on reuse of the input feature map, and a neural network apparatus using the method. The neural network apparatus generates output values of an operation between each of weights of a kernel and an input feature map, and generates an output feature map by accumulating the output values at positions in the output feature map that are set based on positions of the weights in the kernel.

公开(公告)号：US20230169340A1

公开(公告)日：2023-06-01

申请号：US18089696

申请日：2022-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho SONG ,  Namjoon KIM ,  Sehwan LEE ,  Deokjin JOO

IPC: G06N3/08 ,  G06F7/74 ,  G06N20/00

CPC classification number: G06N3/08 ,  G06F7/74 ,  G06N20/00

Abstract: A processor-implemented method of performing convolution operations in a neural network includes generating a plurality of first sub-bit groups and a plurality of second sub-bit groups, respectively from at least one pixel value of an input feature map and at least one predetermined weight, performing a convolution operation on a first pair that includes a first sub-bit group including a most significant bit (MSB) of the at least one pixel value and a second sub-bit group including an MSB of the at least one predetermined weight, based on the plurality of second sub-bit groups, obtaining a maximum value of a sum of results for convolution operations of remaining pairs excepting the first pair, and based on a result of the convolution operation on the first pair and the maximum value, determining whether to perform the convolution operations of the remaining pairs.

公开(公告)号：US20220269950A1

公开(公告)日：2022-08-25

申请号：US17397082

申请日：2021-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan LEE

IPC: G06N3/10 ,  G06N3/04

Abstract: A neural network operation device includes an input feature map buffer to store an input feature map, a weight buffer to store a weight, an operator including an adder tree unit to perform an operation between the input feature map and the weight by a unit of a reference bit length, and a controller to map the input feature map and the weight to the operator to provide one or both of a mixed precision operation and data parallelism.

公开(公告)号：US20220164289A1

公开(公告)日：2022-05-26

申请号：US17317339

申请日：2021-05-11

Applicant: Samsung Electronics Co., Ltd

Inventor： Yoojin KIM ,  Channoh KIM ,  Hyun Sun PARK ,  Sehwan LEE ,  Jun-Woo JANG

IPC: G06F12/0862 ,  G06F12/0804

Abstract: A computing method and device with data sharing re provided. The method includes loading, by a loader, input data of an input feature map stored in a memory in loading units according to a loading order, storing, by a buffer controller, the loaded input data in a reuse buffer of an address rotationally allocated according to the loading order, and transmitting, by each of a plurality of senders, to an executer respective input data corresponding to each output data of respective convolution operations among the input data stored in the reuse buffer, wherein portions of the transmitted respective input data overlap other.

公开(公告)号：US20210150313A1

公开(公告)日：2021-05-20

申请号：US17098589

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Arnab ROY ,  Saptarsi DAS ,  Ankur DESHWAL ,  Kiran Kolar CHANDRASEK HARAN ,  Sehwan LEE

IPC: G06N3/04 ,  G06F7/544

Abstract: A method for computing an inner product on a binary data, a ternary data, a non-binary data, and a non-ternary data using an electronic device. The method includes calculating the inner product on a ternary data, designing a fused bitwise data path to support the inner product calculation on the binary data and the ternary data, designing a FPL data path to calculate an inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data, and distributing the inner product calculation for the binary data and the ternary data and the inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data in the fused bitwise data path and the FPL data path.

公开(公告)号：US20200250842A1

公开(公告)日：2020-08-06

申请号：US16564215

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan LEE

IPC: G06T7/33 ,  G06N3/08 ,  G06T1/20

Abstract: A neural network apparatus includes one or more processors comprising: a controller configured to determine a shared operand to be shared in parallelized operations as being either one of a pixel value among pixel values of an input feature map and a weight value among weight values of a kernel, based on either one or both of a feature of the input feature map and a feature of the kernel; and one or more processing units configured to perform the parallelized operations based on the determined shared operand.

公开(公告)号：US20240232091A1

公开(公告)日：2024-07-11

申请号：US18618355

申请日：2024-03-27

Applicant: Samsung Electronics Co., Ltd

Inventor： Yoojin KIM ,  Channoh KIM ,  Hyun Sun PARK ,  Sehwan LEE ,  Jun-Woo JANG

IPC: G06F12/0862 ,  G06F12/0804 ,  G06F1/04 ,  G06N3/04

CPC classification number: G06F12/0862 ,  G06F12/0804 ,  G06F1/04 ,  G06F2212/1021 ,  G06N3/04

Abstract: A computing method and device with data sharing re provided. The method includes loading, by a loader, input data of an input feature map stored in a memory in loading units according to a loading order, storing, by a buffer controller, the loaded input data in a reuse buffer of an address rotationally allocated according to the loading order, and transmitting, by each of a plurality of senders, to an executer respective input data corresponding to each output data of respective convolution operations among the input data stored in the reuse buffer, wherein portions of the transmitted respective input data overlap other.

公开(公告)号：US20240112030A1

公开(公告)日：2024-04-04

申请号：US18529620

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhaeng LEE ,  Hyunsun PARK ,  Sehwan LEE ,  Seungwon LEE

IPC: G06N3/08 ,  G06N3/0495

CPC classification number: G06N3/08 ,  G06N3/0495

Abstract: A neural network method and apparatus is provided. A processor-implemented neural network method includes a processor and a memory storing information, including stored predetermined precision parameters of a layer of a n neural network, about the layer, the method includes obtaining information about the layer in the memory indicative of the number of output classes; determining, based on the obtained information, a precision for the layer based on the number of output classes of the layer, wherein the precision is determined proportionally with respect to the obtained number of output classes; and processing new parameters, with a set precision, for the layer based on the stored parameter.

公开(公告)号：US20230325462A1

公开(公告)日：2023-10-12

申请号：US18296165

申请日：2023-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gopinath Vasanth MAHALE ,  Pramod Parameshwara UDUPA ,  Jun-Woo JANG ,  Kiran Kolar CHANDRASEKHARAN ,  Sehwan LEE

IPC: G06F17/14 ,  G06N3/0464 ,  G06F7/544

CPC classification number: G06F17/14 ,  G06N3/0464 ,  G06F7/5443

Abstract: A processor-implemented apparatus includes a forward transform module configured to transform input feature maps (IFMs) by performing a forward transform operation in a Winograd convolution (WinConv) domain, multiply and accumulate array (MAA) units configured to multiply the transformed IFMs by transformed kernels and perform a first inverse transform operation based on results of the multiplying, and an inverse transform module configured to generate output feature maps (OFMs) based on a result of the first inverse transform operation.