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公开(公告)号：US11429310B2
公开(公告)日：2022-08-30
申请号：US16914151
申请日：2020-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi
IPC: G06F3/06
Abstract: A method for in-memory computing. In some embodiments, the method includes: executing, by a first function-in-memory circuit, a first instruction, to produce, as a result, a first value, wherein a first computing task includes a second computing task and a third computing task, the second computing task including the first instruction; storing, by the first function-in-memory circuit, the first value in a first buffer; reading, by a second function-in-memory circuit, the first value from the first buffer; and executing, by a second function-in-memory circuit, a second instruction, the second instruction using the first value as an argument, the third computing task including the second instruction, wherein: the storing, by the first function-in-memory circuit, of the first value in the first buffer includes directly storing the first value in the first buffer.
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公开(公告)号：US20220171620A1
公开(公告)日：2022-06-02
申请号：US17548220
申请日：2021-12-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.
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公开(公告)号：US11262980B2
公开(公告)日：2022-03-01
申请号：US16919043
申请日：2020-07-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Peng Gu , Hongzhong Zheng , Robert Brennan
Abstract: A computing accelerator using a lookup table. The accelerator may accelerate floating point multiplications by retrieving the fraction portion of the product of two floating-point operands from a lookup table, or by retrieving the product of two floating-point operands of two floating-point operands from a lookup table, or it may retrieve dot products of floating point vectors from a lookup table. The accelerator may be implemented in a three-dimensional memory assembly. It may use approximation, the symmetry of a multiplication lookup table, and zero-skipping to improve performance.
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公开(公告)号：US11188327B2
公开(公告)日：2021-11-30
申请号：US16823153
申请日：2020-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Peng Gu , Krishna T. Malladi , Hongzhong Zheng
Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.
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公开(公告)号：US11138135B2
公开(公告)日：2021-10-05
申请号：US16194219
申请日：2018-11-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Hongzhong Zheng , Dimin Niu , Peng Gu
Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.
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Patent Agency Ranking
公开(公告)号：US20210294711A1
公开(公告)日：2021-09-23
申请号：US16914119
申请日：2020-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.
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公开(公告)号：US11119677B2
公开(公告)日：2021-09-14
申请号：US15916228
申请日：2018-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Peng Gu , Krishna T. Malladi , Hongzhong Zheng
Abstract: A storage device and method of controlling a storage device are disclosed. The storage device includes a host, a logic die, and a high bandwidth memory stack including a memory die. A computation lookup table is stored on a memory array of the memory die. The host sends a command to perform an operation utilizing a kernel and a plurality of input feature maps, includes finding the product of a weight of the kernel and values of multiple input feature maps. The computation lookup table includes a row corresponding to a weight of the kernel, and a column corresponding to a value of the input feature maps. A result value stored at a position corresponding to a row and a column is the product of the weight corresponding to the row and the value corresponding to the column.
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公开(公告)号：US20200218644A1
公开(公告)日：2020-07-09
申请号：US16823153
申请日：2020-03-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Peng Gu , Krishna T. Malladi , Hongzhong Zheng
Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.
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公开(公告)号：US20180210659A1
公开(公告)日：2018-07-26
申请号：US15470261
申请日：2017-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Hongzhong Zheng
IPC: G06F3/06
CPC classification number: G06F12/023 , G06F2212/1044
Abstract: A method of dynamically selecting deduplication granularity in a memory system to decrease deduplication granularity and to increase hash-table efficiency, the method including selecting one or more deduplication granularities at an application level of an application using the memory system, the one or more deduplication granularities being selected according to features of the memory system, and assigning a memory region corresponding to each of the one or more selected deduplication granularities, where the method may use a memory manager to share memory translation table and hash table, and may be employed by a system that enables using higher capacity pre-allocated counter fields for frequently utilized lines.
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公开(公告)号：US20180189132A1
公开(公告)日：2018-07-05
申请号：US15470657
申请日：2017-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Hongzhong Zheng
CPC classification number: G06F11/1012 , G06F21/64 , G11C29/74 , G11C2029/0409 , G11C2029/0411 , G11C2029/4402
Abstract: A method of performing memory deduplication and single error correction double error detection (SEC-DED) in a computer memory, the method including reading data from an array of memory chips, calculating at least one hash based on the data, checking the one or more hashes against at least one of a physical line ID hash and against a secondary hash, determining whether an error is detected, when an error is detected, correcting the data by changing each bit of the array of the memory chips one at a time until no error is detected, wherein between changing each bit, at least one hash is calculated based on the changed data, and the one or more hash for the new data is compared against one or more of a physical line ID hash and against a secondary hash, and again determining whether an error is detected, and outputting the corrected data when no error is detected.
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