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公开(公告)号：US20220206917A1
公开(公告)日：2022-06-30
申请号：US17699679
申请日：2022-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.
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公开(公告)号：US11226816B2
公开(公告)日：2022-01-18
申请号：US16859829
申请日：2020-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.
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公开(公告)号：US12236239B2
公开(公告)日：2025-02-25
申请号：US18368515
申请日：2023-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.
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公开(公告)号：US11782707B2
公开(公告)日：2023-10-10
申请号：US17548220
申请日：2021-12-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
CPC classification number: G06F9/3001 , G06F7/5318 , G06F7/57 , G06F9/3016 , G06F9/30036 , G06F9/30098
Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.
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公开(公告)号：US20240004646A1
公开(公告)日：2024-01-04
申请号：US18368515
申请日：2023-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
CPC classification number: G06F9/3001 , G06F9/30036 , G06F7/57 , G06F9/30098 , G06F7/5318 , G06F9/3016
Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.
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Patent Agency Ranking
公开(公告)号：US20220171620A1
公开(公告)日：2022-06-02
申请号：US17548220
申请日：2021-12-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.
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公开(公告)号：US20210294711A1
公开(公告)日：2021-09-23
申请号：US16914119
申请日：2020-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.
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公开(公告)号：US20240086292A1
公开(公告)日：2024-03-14
申请号：US18513111
申请日：2023-11-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
CPC classification number: G06F11/3037 , G06F11/3428
Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.
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公开(公告)号：US11853186B2
公开(公告)日：2023-12-26
申请号：US17699679
申请日：2022-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
CPC classification number: G06F11/3037 , G06F11/3428
Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.
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公开(公告)号：US11281554B2
公开(公告)日：2022-03-22
申请号：US16914119
申请日：2020-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.
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