公开(公告)号：US11355181B2

公开(公告)日：2022-06-07

申请号：US17333366

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung Kim ,  Sukhan Lee

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G06F9/30 ,  G06F9/38

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

公开(公告)号：US11158357B2

公开(公告)日：2021-10-26

申请号：US16813851

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Soo Yu ,  Namsung Kim ,  Kyomin Sohn ,  Seongil O ,  Sukhan Lee

IPC: G11C7/10 ,  G11C11/40 ,  G11C5/02 ,  G11C11/408 ,  G11C11/409

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

公开(公告)号：US11069400B1

公开(公告)日：2021-07-20

申请号：US16925049

申请日：2020-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung Kim ,  Sukhan Lee

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G06F9/30 ,  G06F9/38

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.