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    Semiconductor light emitting device
    3.
    发明授权
    Semiconductor light emitting device 有权

    公开(公告)号：US11646398B2

    公开(公告)日：2023-05-09

    申请号：US17323042

    申请日：2021-05-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiwon Park ,  Namsung Kim ,  Youngsub Shin ,  Jonghyun Lee ,  Daemyung Chun ,  Byungchul Choi

    IPC: H01L33/50 ,  H01L33/46 ,  H01L33/38 ,  H01L27/15 ,  H01L33/00

    CPC classification number: H01L33/505 ,  H01L27/15 ,  H01L33/007 ,  H01L33/0093 ,  H01L33/382 ,  H01L33/46 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0041

    Abstract: A semiconductor light emitting device including a semiconductor laminate having first and second surfaces, the semiconductor laminate including first and second conductivity-type semiconductor layers, and an active layer between the semiconductor layers; a partition structure on the first surface, the partition structure having a window defining a light emitting region of the first surface of the semiconductor laminate; a wavelength converter in the window, the wavelength converter being configured to convert a wavelength of light emitted from the active layer; and a first electrode and a second electrode on the second surface of the semiconductor laminate and respectively connected to the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the semiconductor laminate includes a plurality of first patterns arranged in the light emitting region of the first surface, and a plurality of second patterns arranged in a covered region of the first surface contacting the partition structure.

    Semiconductor memory devices
    5.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11366716B2

    公开(公告)日：2022-06-21

    申请号：US17088900

    申请日：2020-11-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yesin Ryu ,  Namsung Kim ,  Sanguhn Cha ,  Jaeyoun Youn ,  Kijun Lee

    IPC: G06F11/10 ,  H01L25/065

    Abstract: A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

    SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING BUFFER STRUCTURE
    6.
    发明申请
    SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING BUFFER STRUCTURE 有权

    公开(公告)号：US20210367102A1

    公开(公告)日：2021-11-25

    申请号：US17117298

    申请日：2020-12-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaiwon Jean ,  Joongseo Kang ,  Namsung Kim ,  Daemyung Chun

    IPC: H01L33/12 ,  H01L33/22 ,  H01L27/15

    Abstract: A semiconductor light-emitting device includes a buffer structure, a first-type semiconductor layer on the buffer structure, an active layer on the first-type semiconductor layer, and a second-type semiconductor layer on the active layer. The buffer structure includes a nucleation layer, a first dislocation-removing structure on the nucleation layer, and a buffer layer on the first dislocation-removing structure. The first dislocation-removing structure includes a first material layer on the nucleation layer and a second material layer on the first material layer. The second material layer has a lattice constant different from a lattice constant of the first material layer. A roughness of a top surface of the first material layer is higher than a roughness of a top surface of the nucleation layer and higher than a roughness of a top surface of the second material layer.

    Memory device for processing operation and method of operating the same
    7.
    发明授权
    Memory device for processing operation and method of operating the same 有权

    公开(公告)号：US11094371B2

    公开(公告)日：2021-08-17

    申请号：US16810344

    申请日：2020-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongil O ,  Shinhaeng Kang ,  Namsung Kim ,  Kyomin Sohn ,  Sukhan Lee

    IPC: G11C11/409 ,  G11C11/4096 ,  G06N3/063 ,  G06N3/04 ,  G06F13/16

    Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.

    Managing memory device with processor-in-memory circuit to perform memory or processing operation
    10.
    发明授权
    Managing memory device with processor-in-memory circuit to perform memory or processing operation 有权

    公开(公告)号：US11663008B2

    公开(公告)日：2023-05-30

    申请号：US16814462

    申请日：2020-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

    IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

    CPC classification number: G06F9/30145 ,  G06F9/321 ,  G06F15/7821

    Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

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