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21.发明授权Single ended current-sensed bus with novel static power free receiver circuit 失效单端电流检测总线，具有新颖的静态无功接收电路公开(公告)号：US07196548B2
公开(公告)日：2007-03-27
申请号：US10927574
申请日：2004-08-25
IPC分类号： H03K19/094 , H03K17/16
CPC分类号： H03K3/356156 , H03K3/356191
摘要： A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.
摘要翻译： 本文描述了具有新颖的静态无功接收器电路的单端电流感测总线。 在一个实施例中，接收器电路示例包括锁存电路，以在响应于输入的评估阶段期间锁存第一输出和第二输出的值;耦合到锁存电路的预充电电路以预充电锁存电路 以及耦合到预充电电路和锁存电路的静态功耗阻塞（SPDB）电路，以在预充电阶段期间基本上阻止静态功率消散。 还描述了其它方法和装置。
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公开(公告)号：US06614279B2
公开(公告)日：2003-09-02
申请号：US09941457
申请日：2001-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
摘要翻译： 时钟接收器电路将从差分时钟分配介质接收的低幅度差分时钟信号分量转换成全摆幅数字时钟。 时钟接收器电路可以用作例如微电子器件内的管芯上的相关时钟分配系统的一部分。
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公开(公告)号：US06522186B2
公开(公告)日：2003-02-18
申请号：US09893067
申请日：2001-06-27
IPC分类号： G06F104
CPC分类号： G06F1/10
摘要： A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.
摘要翻译： 分层时钟分配系统包括将时钟信号分配到多个区域时钟网格的全局时钟网格。 然后，每个区域时钟网格将信号分配给多个对应的负载。 区域时钟网格利用相关的时钟技术将时钟信号分配给相应的负载。 基于时钟信号的周期性，全球电网实现了低偏移，而不是驻波的优势。 区域时钟网格内的终端电气距离优选保持较低，以避免在区域网格上发生相变区域。 在一种方法中，区域网格以对称方式被驱动在多个点，以减少到终止的电距离。
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公开(公告)号：US07352209B2
公开(公告)日：2008-04-01
申请号：US11411647
申请日：2006-04-26
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
摘要翻译： 电压电平转换器包括静态电压电平转换器和耦合到静态电压电平转换器的分离电平输出电路。 在另一实施例中，电压电平转换器包括静态电压电平转换器，第一晶体管和第二晶体管。 静态电压电平转换器包括输入节点，第一上拉节点，第二上拉节点，逆变器输出节点和输出节点。 第一晶体管耦合到输入节点和第一上拉节点。 第二晶体管耦合到第二上拉节点和逆变器输出节点。
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公开(公告)号：US07272029B2
公开(公告)日：2007-09-18
申请号：US11025778
申请日：2004-12-29
IPC分类号： G11C11/00
摘要： A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
摘要翻译： 读出放大器转换将输出信号编码到总线上，使得当感测到的位线具有与先前感测的位线的状态不同的状态时，总线信号仅转变。 读出放大器包括当总线信号被断言时改变状态的存储元件。 基于存储元件的状态，读出放大器的输出有条件地反转。
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公开(公告)号：US06909127B2
公开(公告)日：2005-06-21
申请号：US09893023
申请日：2001-06-27
IPC分类号： H01L23/522 , H01L27/10
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
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