-
公开(公告)号：US06909127B2
公开(公告)日：2005-06-21
申请号：US09893023
申请日：2001-06-27
IPC分类号： H01L23/522 , H01L27/10
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
-
公开(公告)号：US07352059B2
公开(公告)日：2008-04-01
申请号：US11152643
申请日：2005-06-14
IPC分类号： H01L27/10 , H01L23/52 , H01L23/522 , H01R12/00
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
摘要翻译： 低损耗管芯互连结构包括在微电子管芯的金属层之一上的第一和第二差分信号线。 还可以在与差分信号线不平行（例如，正交））的管芯的另一金属层上提供一个或多个迹线。 由于迹线不平行，它们为差分信号线上的信号提供了相对较高的阻抗返回路径。 因此，通过相反的微分线路的信号返回路径对于差分线路上的信号占优势。 在一个应用中，低损耗互连结构用于管芯内的相关时钟分配网络。
-
公开(公告)号：US06522186B2
公开(公告)日：2003-02-18
申请号：US09893067
申请日：2001-06-27
IPC分类号： G06F104
CPC分类号： G06F1/10
摘要： A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.
摘要翻译： 分层时钟分配系统包括将时钟信号分配到多个区域时钟网格的全局时钟网格。 然后，每个区域时钟网格将信号分配给多个对应的负载。 区域时钟网格利用相关的时钟技术将时钟信号分配给相应的负载。 基于时钟信号的周期性，全球电网实现了低偏移，而不是驻波的优势。 区域时钟网格内的终端电气距离优选保持较低，以避免在区域网格上发生相变区域。 在一种方法中，区域网格以对称方式被驱动在多个点，以减少到终止的电距离。
-
公开(公告)号：US06828841B2
公开(公告)日：2004-12-07
申请号：US10652668
申请日：2003-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
-
公开(公告)号：US06225826B1
公开(公告)日：2001-05-01
申请号：US09220816
申请日：1998-12-23
IPC分类号： H03K19096
CPC分类号： H03K19/096 , H03K19/0963
摘要： In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal. The dual function generator is a single ended domino compatible dual function generator to provide an out signal and an out* signal that each have a state and during a precharge phase, the out signal and out* signal each have the same state, and during an evaluate phase the out and out* states are complementary states as a function of the domino stage input signal without a logic X circuit and a logic X* circuit.
摘要翻译： 在一些实施例中，本发明包括具有多米诺骨架状态和单端多米诺骨牌兼容双功能发生器的多米诺逻辑门电路。 多米诺骨牌状态接收多米诺骨牌级输入信号，并提供作为多米诺骨牌级输入信号的函数的单端中间信号，中间信号具有状态。 发生器接收中间信号并提供各自具有状态的输出信号和输出信号，其中输出和输出信号在预充电阶段期间具有相同的状态，并且在作为状态的函数的评估阶段期间具有互补状态 的中间信号。 在其他实施例中，本发明包括具有组合多米诺舞台和双功能发生器的多米诺逻辑门电路。 多米诺骨牌阶段是接收多米诺骨牌阶段的输入信号。 双功能发生器是单端多米诺骨牌兼容双功能发生器，用于提供每个具有状态的输出信号和输出信号，并且在预充电阶段期间，输出信号和输出信号各自具有相同的状态，并且在 评估相位，out和out *状态是互补状态，作为多米诺舞台输入信号的函数，没有逻辑X电路和逻辑X *电路。
-
公开(公告)号：US06614279B2
公开(公告)日：2003-09-02
申请号：US09941457
申请日：2001-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
摘要翻译： 时钟接收器电路将从差分时钟分配介质接收的低幅度差分时钟信号分量转换成全摆幅数字时钟。 时钟接收器电路可以用作例如微电子器件内的管芯上的相关时钟分配系统的一部分。
-
公开(公告)号：US07519646B2
公开(公告)日：2009-04-14
申请号：US11586810
申请日：2006-10-26
申请人： Himanshu Kaul , Mark A. Anders , Sanu Mathew , Ram Krishnamurthy
发明人： Himanshu Kaul , Mark A. Anders , Sanu Mathew , Ram Krishnamurthy
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F2207/3828
摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.
摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。
-
公开(公告)号：US07380099B2
公开(公告)日：2008-05-27
申请号：US10956164
申请日：2004-09-30
IPC分类号： G06F12/00
摘要： A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.
摘要翻译： 一种用于地址产生电路的方法和装置。 在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。 一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。 随后，从多个条件和中选出一个和，以在第二阶段中的第一阶段的逻辑地址分量和有效地址的第二部分中形成有效地址的第一部分。 在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。 描述和要求保护其他实施例。
-
9.发明申请METHOD, APPARATUS AND SYSTEM FOR A SOURCE-SYNCHRONOUS CIRCUIT-SWITCHED NETWORK ON A CHIP (NOC) 有权用于芯片上同步电路切换网络的方法，装置和系统（NOC）公开(公告)号：US20150220470A1
公开(公告)日：2015-08-06
申请号：US14126910
申请日：2013-06-28
CPC分类号： G06F13/4022 , G06F13/4282 , G06F15/7825 , H04L12/46 , H04L49/109 , H04L67/10 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，路由器包括多个输入端口和输出端口，其中路由器是源同步混合网络片上（NoC），以基于在路由器之间传送的控制流信号中的转换来实现NoC的路由器之间的通信。 描述和要求保护其他实施例。
-
公开(公告)号：US07196546B2
公开(公告)日：2007-03-27
申请号：US10748833
申请日：2003-12-30
申请人： Mark A. Anders , Peter Caputa , Ram Krishnamurthy
发明人： Mark A. Anders , Peter Caputa , Ram Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K3/356139 , H04L25/028 , H04L25/0292
摘要： According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.
摘要翻译： 根据一些实施例，提供了一种用于接收全摆幅输入信号，将全摆幅输入信号转换为低摆幅信号并传输低回转信号的静态低摆幅驱动器电路，以及动态 接收器电路来接收低摆动信号并将低摆幅信号转换成全摆幅信号。 还可以提供耦合到驱动器电路和接收器电路的互连，互连不包括中继器并且接收来自驱动器电路的低摆动信号并且将低回转信号发送到接收器电路。
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.019 秒)