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公开(公告)号：US07352209B2
公开(公告)日：2008-04-01
申请号：US11411647
申请日：2006-04-26
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
摘要翻译： 电压电平转换器包括静态电压电平转换器和耦合到静态电压电平转换器的分离电平输出电路。 在另一实施例中，电压电平转换器包括静态电压电平转换器，第一晶体管和第二晶体管。 静态电压电平转换器包括输入节点，第一上拉节点，第二上拉节点，逆变器输出节点和输出节点。 第一晶体管耦合到输入节点和第一上拉节点。 第二晶体管耦合到第二上拉节点和逆变器输出节点。
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公开(公告)号：US07272029B2
公开(公告)日：2007-09-18
申请号：US11025778
申请日：2004-12-29
IPC分类号： G11C11/00
摘要： A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
摘要翻译： 读出放大器转换将输出信号编码到总线上，使得当感测到的位线具有与先前感测的位线的状态不同的状态时，总线信号仅转变。 读出放大器包括当总线信号被断言时改变状态的存储元件。 基于存储元件的状态，读出放大器的输出有条件地反转。
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公开(公告)号：US06628143B2
公开(公告)日：2003-09-30
申请号：US09965360
申请日：2001-09-26
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.
摘要翻译： 全驱动，源极跟随器泄漏容限动态逻辑门的实施例包括nMOSFET逻辑，用于在评估阶段对节点进行有条件充电，并且在预充电阶段期间将节点充电至相对小的电压，使得nMOSFET 逻辑变为反向偏置。
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公开(公告)号：US06828841B2
公开(公告)日：2004-12-07
申请号：US10652668
申请日：2003-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
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公开(公告)号：US06225826B1
公开(公告)日：2001-05-01
申请号：US09220816
申请日：1998-12-23
IPC分类号： H03K19096
CPC分类号： H03K19/096 , H03K19/0963
摘要： In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal. The dual function generator is a single ended domino compatible dual function generator to provide an out signal and an out* signal that each have a state and during a precharge phase, the out signal and out* signal each have the same state, and during an evaluate phase the out and out* states are complementary states as a function of the domino stage input signal without a logic X circuit and a logic X* circuit.
摘要翻译： 在一些实施例中，本发明包括具有多米诺骨架状态和单端多米诺骨牌兼容双功能发生器的多米诺逻辑门电路。 多米诺骨牌状态接收多米诺骨牌级输入信号，并提供作为多米诺骨牌级输入信号的函数的单端中间信号，中间信号具有状态。 发生器接收中间信号并提供各自具有状态的输出信号和输出信号，其中输出和输出信号在预充电阶段期间具有相同的状态，并且在作为状态的函数的评估阶段期间具有互补状态 的中间信号。 在其他实施例中，本发明包括具有组合多米诺舞台和双功能发生器的多米诺逻辑门电路。 多米诺骨牌阶段是接收多米诺骨牌阶段的输入信号。 双功能发生器是单端多米诺骨牌兼容双功能发生器，用于提供每个具有状态的输出信号和输出信号，并且在预充电阶段期间，输出信号和输出信号各自具有相同的状态，并且在 评估相位，out和out *状态是互补状态，作为多米诺舞台输入信号的函数，没有逻辑X电路和逻辑X *电路。
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6.发明申请ARCHITECTURE AND METHOD FOR HYBRID CIRCUIT-SWITCHED AND PACKET-SWITCHED ROUTER 有权用于混合电路切换和分组交换路由器的架构和方法公开(公告)号：US20150071282A1
公开(公告)日：2015-03-12
申请号：US14129544
申请日：2013-09-06
IPC分类号： H04L12/64
CPC分类号： H04L12/6418 , G06F15/7825 , H04L49/109 , H04L49/251 , H04L49/252 , H04L49/9042
摘要： Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.
摘要翻译： 用于执行电路交换路由和分组交换路由以用于网络通信的技术和机制。 在一个实施例中，路由器评估由路由器接收的分组的控制信息，评估以检测分组是否包括用于边带通信的数据。 基于该评估，路由器从路由器的多个模式中进行选择，该多个模式包括在网络中路由用于边带数据的分组交换通信的分组的第一模式。 多个模式还包括根据分组配置电路交换信道的第二模式。 在另一个实施例中，路由器确定用于在分层网络中路由分组的方向，其中所述方向的确定基于所述分级网络的层级中的路由器的级别。
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公开(公告)号：US07325024B2
公开(公告)日：2008-01-29
申请号：US10728127
申请日：2003-12-04
IPC分类号： G06F7/50
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译： 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。
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8.发明授权公开(公告)号：US06351150B1
公开(公告)日：2002-02-26
申请号：US09658793
申请日：2000-09-11
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/01855
摘要： A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.
摘要翻译： 利用动态驱动技术的高性能互连能够在低数据交换活动期间降低功耗。 提供了电路，其将动态驱动器电路中的评估操作的性能限制为时钟周期，在该周期期间，互连的当前输入位与先前的输入位不同。 因此，在低数据切换活动的时段期间，谨慎地执行驱动器输出的评估操作和随后的预充电。 还提供了一个输出电路，用于解码在其接收端处流经互连的数据流。 使用本发明的原理，可以通过使用静态CMOS技术的互连的交换活动来实现动态驱动器的性能优点。
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9.发明申请METHOD, APPARATUS AND SYSTEM FOR A SOURCE-SYNCHRONOUS CIRCUIT-SWITCHED NETWORK ON A CHIP (NOC) 有权用于芯片上同步电路切换网络的方法，装置和系统（NOC）公开(公告)号：US20150220470A1
公开(公告)日：2015-08-06
申请号：US14126910
申请日：2013-06-28
CPC分类号： G06F13/4022 , G06F13/4282 , G06F15/7825 , H04L12/46 , H04L49/109 , H04L67/10 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，路由器包括多个输入端口和输出端口，其中路由器是源同步混合网络片上（NoC），以基于在路由器之间传送的控制流信号中的转换来实现NoC的路由器之间的通信。 描述和要求保护其他实施例。
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公开(公告)号：US20140105303A1
公开(公告)日：2014-04-17
申请号：US13649560
申请日：2012-10-11
IPC分类号： H04N7/32
CPC分类号： H04N19/43 , H04N19/567
摘要： In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.
摘要翻译： 根据一些实施例，可以减少使用Haar，SAD和Hadamard变换的运动估计算法的复杂度。 在一些实施例中，与现有技术相比可以减少求和的数量，并且可以用比较操作来替换一些现有的求和。 在一些实施例中，为了平衡延迟和面积或能量或功率考虑，用比较代替添加。
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