-
公开(公告)号：US06909127B2
公开(公告)日：2005-06-21
申请号：US09893023
申请日：2001-06-27
IPC分类号： H01L23/522 , H01L27/10
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
-
公开(公告)号：US07352059B2
公开(公告)日：2008-04-01
申请号：US11152643
申请日：2005-06-14
IPC分类号： H01L27/10 , H01L23/52 , H01L23/522 , H01R12/00
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
摘要翻译： 低损耗管芯互连结构包括在微电子管芯的金属层之一上的第一和第二差分信号线。 还可以在与差分信号线不平行（例如，正交））的管芯的另一金属层上提供一个或多个迹线。 由于迹线不平行，它们为差分信号线上的信号提供了相对较高的阻抗返回路径。 因此，通过相反的微分线路的信号返回路径对于差分线路上的信号占优势。 在一个应用中，低损耗互连结构用于管芯内的相关时钟分配网络。
-
公开(公告)号：US06522186B2
公开(公告)日：2003-02-18
申请号：US09893067
申请日：2001-06-27
IPC分类号： G06F104
CPC分类号： G06F1/10
摘要： A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.
摘要翻译： 分层时钟分配系统包括将时钟信号分配到多个区域时钟网格的全局时钟网格。 然后，每个区域时钟网格将信号分配给多个对应的负载。 区域时钟网格利用相关的时钟技术将时钟信号分配给相应的负载。 基于时钟信号的周期性，全球电网实现了低偏移，而不是驻波的优势。 区域时钟网格内的终端电气距离优选保持较低，以避免在区域网格上发生相变区域。 在一种方法中，区域网格以对称方式被驱动在多个点，以减少到终止的电距离。
-
公开(公告)号：US06828841B2
公开(公告)日：2004-12-07
申请号：US10652668
申请日：2003-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
-
公开(公告)号：US06225826B1
公开(公告)日：2001-05-01
申请号：US09220816
申请日：1998-12-23
IPC分类号： H03K19096
CPC分类号： H03K19/096 , H03K19/0963
摘要： In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal. The dual function generator is a single ended domino compatible dual function generator to provide an out signal and an out* signal that each have a state and during a precharge phase, the out signal and out* signal each have the same state, and during an evaluate phase the out and out* states are complementary states as a function of the domino stage input signal without a logic X circuit and a logic X* circuit.
摘要翻译： 在一些实施例中，本发明包括具有多米诺骨架状态和单端多米诺骨牌兼容双功能发生器的多米诺逻辑门电路。 多米诺骨牌状态接收多米诺骨牌级输入信号，并提供作为多米诺骨牌级输入信号的函数的单端中间信号，中间信号具有状态。 发生器接收中间信号并提供各自具有状态的输出信号和输出信号，其中输出和输出信号在预充电阶段期间具有相同的状态，并且在作为状态的函数的评估阶段期间具有互补状态 的中间信号。 在其他实施例中，本发明包括具有组合多米诺舞台和双功能发生器的多米诺逻辑门电路。 多米诺骨牌阶段是接收多米诺骨牌阶段的输入信号。 双功能发生器是单端多米诺骨牌兼容双功能发生器，用于提供每个具有状态的输出信号和输出信号，并且在预充电阶段期间，输出信号和输出信号各自具有相同的状态，并且在 评估相位，out和out *状态是互补状态，作为多米诺舞台输入信号的函数，没有逻辑X电路和逻辑X *电路。
-
公开(公告)号：US20050227507A1
公开(公告)日：2005-10-13
申请号：US11152643
申请日：2005-06-14
IPC分类号： H01L23/522 , H01R12/00
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
摘要翻译： 低损耗管芯互连结构包括在微电子管芯的金属层之一上的第一和第二差分信号线。 还可以在与差分信号线不平行（例如，正交））的管芯的另一金属层上提供一个或多个迹线。 由于迹线不平行，它们为差分信号线上的信号提供了相对较高的阻抗返回路径。 因此，通过相反的微分线路的信号返回路径对于差分线路上的信号占优势。 在一个应用中，低损耗互连结构用于管芯内的相关时钟分配网络。
-
公开(公告)号：US06614279B2
公开(公告)日：2003-09-02
申请号：US09941457
申请日：2001-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
摘要翻译： 时钟接收器电路将从差分时钟分配介质接收的低幅度差分时钟信号分量转换成全摆幅数字时钟。 时钟接收器电路可以用作例如微电子器件内的管芯上的相关时钟分配系统的一部分。
-
8.发明申请PROGRAMMABLE ENGINE HAVING A RECONFIGURABLE ACCELERATOR DATA PATH FOR TESTING AND CALIBRATION OF ANALOG FRONT ENDS IN RADIO DEVICES 有权具有可重构加速器数据路径的可编程发动机，用于在无线电设备中测试和校准模拟前端公开(公告)号：US20120099630A1
公开(公告)日：2012-04-26
申请号：US12910129
申请日：2010-10-22
IPC分类号： H04B17/00
CPC分类号： H04B17/16
摘要： Briefly, in accordance with one or more embodiments, a radio device comprises an analog front end comprising a radio to transmit and/or receive radio-frequency signals, and a programmable engine coupled to the analog front end. The programmable engine is capable of being programmed to perform one or more tests on the analog front end and includes a reconfigurable data path reconfigurable by the programmable engine to perform one or more tests on the analog front end.
摘要翻译： 简而言之，根据一个或多个实施例，无线电设备包括模拟前端，其包括用于发射和/或接收射频信号的无线电装置，以及耦合到模拟前端的可编程引擎。 可编程引擎能够被编程为对模拟前端执行一个或多个测试，并且包括由可编程引擎重新配置以在模拟前端执行一个或多个测试的可重构数据路径。
-
公开(公告)号：US07565393B2
公开(公告)日：2009-07-21
申请号：US11169808
申请日：2005-06-29
IPC分类号： G06G7/02
CPC分类号： H03H15/00
摘要： A discrete time filter achieves gain by sampling a signal using capacitors arranged in a one configuration and then changing the capacitors to a series configuration to develop a filter output voltage. In at least one embodiment, a variable gain filter is achieved by varying the number of capacitors that are active in the filter.
摘要翻译： 离散时间滤波器通过使用以一种配置布置的电容器对信号进行采样，然后将电容器改变为串联配置来产生滤波器输出电压来实现增益。 在至少一个实施例中，通过改变在滤波器中有效的电容器的数量来实现可变增益滤波器。
-
10.发明申请System and Method for Controlling Resonance Frequency of Film Bulk Acoustic Resonator Devices 有权用于控制膜体积声谐振器器件的谐振频率的系统和方法公开(公告)号：US20090039981A1
公开(公告)日：2009-02-12
申请号：US11836538
申请日：2007-08-09
IPC分类号： H03H9/13
CPC分类号： H03H19/004 , H03H9/02007 , H03H2009/02204
摘要： Disclosed is a system and method for controlling a resonance frequency of a Film Bulk Acoustic Resonator (FBAR) device. The system includes at least one switching capacitor coupled to the FBAR device and a modulator. The at least one switching capacitor includes at least one capacitor and a switch configuration disposed in series with the FBAR device and the at least one capacitor, which is switch configuration capable of opening and closing connection of the at least one capacitor with the FBAR device. The modulator is coupled to the switch configuration, which generates a switching condition signal based on the manufacturing variation in the FBAR device and the environmental effects on the FBAR device. The switch configuration performs opening and closing of the connection of the at least one capacitor and the FBAR device based on the switching condition signal.
摘要翻译： 公开了一种用于控制膜体声波谐振器（FBAR）装置的谐振频率的系统和方法。 该系统包括耦合到FBAR器件和调制器的至少一个开关电容器。 所述至少一个开关电容器包括至少一个电容器和与所述FBAR器件和所述至少一个电容器串联布置的开关配置，所述至少一个电容器是能够打开和关闭所述至少一个电容器与所述FBAR器件的连接的开关配置。 调制器耦合到开关配置，其根据FBAR器件的制造变化和对FBAR器件的环境影响产生开关条件信号。 开关配置基于开关条件信号来执行至少一个电容器和FBAR器件的连接的打开和闭合。
-
-
-
-
-
-
-
-
-
搜索结果
54 条记录 (耗时 0.018 秒)