公开(公告)号：US07131081B2

公开(公告)日：2006-10-31

申请号：US10736879

申请日：2003-12-16

Applicant: Seongmoon Wang ,  Srimat Chakradhar

Inventor： Seongmoon Wang ,  Srimat Chakradhar

IPC: G06F17/50

CPC classification number: G01R31/31858 ,  G01R31/318328 ,  G01R31/318583

Abstract: A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain.

Abstract translation: 一种逻辑电路，包括至少一个输入，一个输出和延迟故障电路。 延迟故障电路包括第一标准扫描单元，位于扫描链中的第一标准扫描单元之后的组合测试点和位于扫描链中的组合测试点之后的第二标准扫描单元。

公开(公告)号：US20050066242A1

公开(公告)日：2005-03-24

申请号：US10653959

申请日：2003-09-04

Applicant: Seongmoon Wang ,  Xiao Liu ,  Srimat Chakradhar

Inventor： Seongmoon Wang ,  Xiao Liu ,  Srimat Chakradhar

IPC: G01R31/3185 ,  G06K5/04 ,  G11B5/00 ,  G11B20/18 ,  G11B20/20

CPC classification number: G01R31/31858 ,  G11B20/1816

Abstract: A scan-based method for testing delay faults in a circuit comprising controlling a subset of state inputs of the circuit by a skewed-load approach and controlling all inputs other than said subset of state inputs by a broad-side approach.

Abstract translation: 一种用于测试电路中的延迟故障的基于扫描的方法，包括通过偏斜负载方法控制所述电路的状态输入的子集，并且通过广泛方法控制除所述状态输入子集之外的所有输入。

公开(公告)号：US07818643B2

公开(公告)日：2010-10-19

申请号：US12034088

申请日：2008-02-20

Applicant: Seongmoon Wang ,  Srimat T Chakradhar

Inventor： Seongmoon Wang ,  Srimat T Chakradhar

IPC: G01R31/28

CPC classification number: G01R31/318547

Abstract: A method includes compressing control patterns describing values required at the control signals of blocking logic gates, by linear feedback shift register LFSR reseeding; bypassing blocking logic gates for some groups of scan chains that do not capture unknown values in output response of scan test patterns for testing circuits; and reducing numbers of specified bits in densely specified ones of the control patterns for further reducing the size of a seed of the LFSR.

Abstract translation: 一种方法包括通过线性反馈移位寄存器LFSR重新进给来压缩描述阻塞逻辑门控制信号所需的值的控制模式; 绕过阻塞逻辑门，用于扫描链的扫描测试图形的输出响应中未捕获未知值的扫描链组; 并且减少密集指定的控制模式中的指定位的数量，以进一步减小LFSR的种子的大小。

公开(公告)号：US20100005041A1

公开(公告)日：2010-01-07

申请号：US12269380

申请日：2008-11-12

Applicant: Seongmoon Wang

Inventor： Seongmoon Wang

IPC: G06F15/18 ,  G06F17/50

CPC classification number: G01R31/2894 ,  G06N20/00

Abstract: A system and method for integrated circuit diagnosis includes partitioning an integrated circuit design into sub-regions according to a structure of the integrated circuit design. A decision function is generated for a sub-region by training a machine learning tool. A sequence of test patterns is applied to a device under test (DUT) to determine responses. If the DUT fails, all the decision functions are evaluated with the errors produced by the DUT. A sub-region whose decision function yielded a highest value is selected to find a defect sub-region in the DUT.

Abstract translation: 用于集成电路诊断的系统和方法包括根据集成电路设计的结构将集成电路设计分成子区域。 通过训练机器学习工具为子区域生成决策功能。 测试模式的序列被应用于被测器件（DUT）以确定响应。 如果DUT发生故障，则所有的判决功能都由DUT产生的错误进行评估。 选择其决策函数产生最高值的子区域以在DUT中找到缺陷子区域。

公开(公告)号：US07610540B2

公开(公告)日：2009-10-27

申请号：US12265300

申请日：2008-11-05

Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

IPC: G06F11/00 ,  G06G7/58

CPC classification number: G01R31/31921

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract translation: 公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。 测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。 解压缩器被配置为从种子和扫描输入的位置生成测试图案。 解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。

公开(公告)号：US07577540B2

公开(公告)日：2009-08-18

申请号：US10108476

申请日：2002-03-29

Applicant: Seongmoon Wang ,  Srimat T. Chakradhar ,  Kedarnath J. Balakrishnan

Inventor： Seongmoon Wang ,  Srimat T. Chakradhar ,  Kedarnath J. Balakrishnan

IPC: G01R31/317 ,  G06F11/26

CPC classification number: G06F11/2242

Abstract: A test system for a circuit board , wherein the circuit board has a plurality of cores such that at least one of the plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board. A system-on-chip (SOC) with an embedded test protocol architecture, the SOC comprising at least one embedded core, a communication fabric that connects at least one embedded core, at least one test server; and at least one test client connected to said at least one embedded core and connected to the communication fabric.

Abstract translation: 一种用于电路板的测试系统，其中所述电路板具有多个芯，使得所述多个芯中的至少一个芯适于使用独立于所述电路板中使用的通信结构的测试协议。 一种具有嵌入式测试协议架构的片上系统（SOC），所述SOC包括至少一个嵌入式核心，连接至少一个嵌入式核心的通信结构，至少一个测试服务器; 以及连接到所述至少一个嵌入式核心并连接到所述通信结构的至少一个测试客户端。

公开(公告)号：US20080195904A1

公开(公告)日：2008-08-14

申请号：US12015129

申请日：2008-01-16

Applicant: Seongmoon Wang

Inventor： Seongmoon Wang

IPC: G01R31/3181 ,  G06F11/26

CPC classification number: G01R31/318547

Abstract: A method for increasing fault coverage and compression with a broadcast scan-based test data compression circuit includes inserting test points for breaking correlations existing between scan inputs that belong to same scan slices making some faults un-testable with a broadcast scan-based test data compression circuit; and reordering scan inputs for further reducing correlations between scan inputs that belong to the same scan slices.

Abstract translation: 使用基于广播扫描的测试数据压缩电路来增加故障覆盖和压缩的方法包括：插入测试点，用于破坏属于相同扫描片的扫描输入之间存在的相关性，从而使一些故障与基于广播扫描的测试数据压缩无法测试 电路 并重新排序扫描输入，以进一步减少属于相同扫描片的扫描输入之间的相关性。

公开(公告)号：US20070266283A1

公开(公告)日：2007-11-15

申请号：US11692367

申请日：2007-03-28

Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

IPC: G01R31/28

CPC classification number: G01R31/318547

Abstract: Disclosed is an apparatus and method for testing an IC having a plurality of scan chains. A test input is transmitted over a tester channel to at least one scan chain during a time interval. Specifically, a memory element stores a first test input transmitted during a first time interval and a combinational circuit connected to the memory element and scan chain transmits to the scan chain one of a) the first test input and b) a second test input transmitted over the tester channel during a second time interval occurring after the first time interval.

Abstract translation: 公开了一种用于测试具有多个扫描链的IC的装置和方法。 在一段时间间隔内，测试输入通过测试仪通道发送到至少一个扫描链。 具体地，存储元件存储在第一时间间隔期间发送的第一测试输入和连接到存储元件的组合电路，扫描链将扫描链传送到扫描链a）第一测试输入中的一个，以及b）传输的第二测试输入 在第一时间间隔之后的第二时间间隔期间发生测试仪通道。

公开(公告)号：US07222277B2

公开(公告)日：2007-05-22

申请号：US10985599

申请日：2004-11-10

Applicant: Seongmoon Wang ,  Srimat T. Chakradhar ,  Chia-Tso Chao

Inventor： Seongmoon Wang ,  Srimat T. Chakradhar ,  Chia-Tso Chao

IPC: G01R31/28

CPC classification number: G01R31/318547

Abstract: A test output compaction architecture and method that takes advantage of a response shaper in order to minimize masking of faults during compaction. A response shaper is inserted between a plurality of scan chains and an output compactor. The response shaper receives output responses from scan chains and reshapes the output responses in a manner that minimizes masking of faults by the output compactor.

Abstract translation: 测试输出压缩架构和方法，利用响应整形器，以最大限度地减少压实过程中故障的屏蔽。 响应整形器插入在多个扫描链和输出压实机之间。 响应整形器接收来自扫描链的输出响应，并且以使输出压实机的故障掩蔽最小化的方式重新形成输出响应。

公开(公告)号：US20070088999A1

公开(公告)日：2007-04-19

申请号：US11277782

申请日：2006-03-29

Applicant: Chia-Tso Chao ,  Seongmoon Wang ,  Srimat Chakradhar

Inventor： Chia-Tso Chao ,  Seongmoon Wang ,  Srimat Chakradhar

IPC: G01R31/28

CPC classification number: G01R31/318547

Abstract: A spatial compactor design and technique for the compaction of test response data is herein disclosed which advantageously provides a scan-out response with multiple opportunities to be observed on different output channels in one to several scan-shift cycles.

Abstract translation: 本文公开了用于压缩测试响应数据的空间压实机设计和技术，其有利地提供扫描输出响应，其具有在一到多个扫描移位周期中在不同输出通道上观察到的多个机会。