公开(公告)号：US20210286724A1

公开(公告)日：2021-09-16

申请号：US17332286

申请日：2021-05-27

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/0804 ,  G06F12/128

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.