公开(公告)号：US12248405B2

公开(公告)日：2025-03-11

申请号：US18474411

申请日：2023-09-26

Applicant: SiFive, Inc.

Inventor： Dean Liberty ,  Robert P. Adler ,  Henry Cook ,  Abderrahmane Sensaoui ,  Perrine Peresse

IPC: G06F12/10

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

公开(公告)号：US20240184698A1

公开(公告)日：2024-06-06

申请号：US18341091

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra ,  Eric Andrew Gouldey ,  Michael Klinglesmith ,  Henry Cook

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: A method and apparatus for a cache coherency state request vector is described. A method includes selecting, by a first agent, one or more bits in a cache coherency state request vector, where a selected bit in the cache coherency state request vector indicates an acceptable cache coherency state for a cache block indicated in a request message, transmitting, by the first agent to a second agent, the request message for the cache block, the request message including the cache coherency state request vector, and receiving, by the first agent from the second agent, a response message with a cache coherency response state, wherein the cache coherency response state indicates a cache coherency state responsive to the cache coherency state request vector.

公开(公告)号：US11922101B2

公开(公告)日：2024-03-05

申请号：US18123422

申请日：2023-03-20

Applicant: SiFive, Inc.

Inventor： Yunsup Lee ,  Richard Xia ,  Derek Pappas ,  Mark Nugent ,  Henry Cook ,  Wesley Waylon Terpstra ,  Pin Hung Chen

IPC: G06F30/20 ,  G06F30/30

CPC classification number: G06F30/20 ,  G06F30/30

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

公开(公告)号：US20230029660A1

公开(公告)日：2023-02-02

申请号：US17961137

申请日：2022-10-06

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/0804 ,  G06F12/128

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

公开(公告)号：US20220261522A1

公开(公告)日：2022-08-18

申请号：US17734332

申请日：2022-05-02

Applicant: SiFive, Inc.

Inventor： Henry Cook ,  Ernest L. Edgar ,  Ryan Macdonald ,  Wesley Waylon Terpstra

IPC: G06F30/327 ,  G06F30/333

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

公开(公告)号：US20200042664A1

公开(公告)日：2020-02-06

申请号：US16528911

申请日：2019-08-01

Applicant: SiFive, Inc.

Inventor： Yunsup Lee ,  Richard Xia ,  Derek Pappas ,  Mark Nugent ,  Henry Cook ,  Wesley Waylon Terpstra ,  Pin Hung Chen

IPC: G06F17/50

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

公开(公告)号：US20240338329A1

公开(公告)日：2024-10-10

申请号：US18747410

申请日：2024-06-18

Applicant: SiFive, Inc.

Inventor： Robert P. Adler ,  David Parry ,  Rick H. Y. Chen ,  Henry Cook

IPC: G06F13/16 ,  G06F12/0888

CPC classification number: G06F13/1668 ,  G06F12/0888 ,  G06F2212/603

Abstract: Disclosed are systems and methods that include accessing design parameters to configure an integrated circuit design. The integrated circuit design may include a transaction source or processing node to be included in an integrated circuit. The transaction source or processing node may be configured to transmit memory transactions to memory addresses. A compiler may compile the integrated circuit design with the transaction source or processing node to generate a design output. The design output may be configured to route memory transactions based on their targeting cacheable or non-cacheable memory addresses. The design output may be used to manufacture an integrated circuit.

公开(公告)号：US20240256462A1

公开(公告)日：2024-08-01

申请号：US18474411

申请日：2023-09-26

Applicant: SiFive, Inc.

Inventor： Dean Liberty ,  Robert P. Adler ,  Henry Cook ,  Abderrahmane Sensaoui ,  Perrine Peresse

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

公开(公告)号：US20240211665A1

公开(公告)日：2024-06-27

申请号：US18197422

申请日：2023-05-15

Applicant: SiFive, Inc.

Inventor： Jack Koenig ,  Megan Wachs ,  Henry Cook

IPC: G06F30/327

CPC classification number: G06F30/327

Abstract: A system may provide a placeholder for a component in a block of a first-level integrated circuit design without wiring at least one port of the component. The system may determine a mapping to a provider interface in the block. The system may invoke an integrated circuit generator to generate a second-level integrated circuit design based on the first-level integrated circuit design. The generator when executed replaces the provider interface with the component including wiring ports of the component, including the at least one port, in the second-level integrated circuit design according to the mapping. In some implementations, an application program interface may enable a provider to communicate with the generator. The provider can utilize the API to instantiate the provider interface and determine the mapping.

公开(公告)号：US11675945B2

公开(公告)日：2023-06-13

申请号：US17734332

申请日：2022-05-02

Applicant: SiFive, Inc.

Inventor： Henry Cook ,  Ernest L. Edgar ,  Ryan Macdonald ,  Wesley Waylon Terpstra

IPC: G06F30/327 ,  G06F30/333 ,  G06F30/3312 ,  G06F30/398 ,  G06F30/3315 ,  G06F30/396 ,  G06F119/12 ,  G06F115/02

CPC classification number: G06F30/327 ,  G06F30/333 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/396 ,  G06F30/398 ,  G06F2115/02 ,  G06F2119/12

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.