公开(公告)号：US12248401B2

公开(公告)日：2025-03-11

申请号：US18341244

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F12/0831

Abstract: An agent may be configured to invoke a first eviction operation that is interruptible by probe operations when receiving a first type of eviction message and invoke a second eviction operation in which probe operations are interruptible by the second eviction operation when receiving a second type of eviction message. In some implementations, the agent may maintain a data storage that is inclusive of at least one of unique or dirty cache blocks in a cache maintained by an agent that transmits the second type of eviction message. In some implementations, the agent may prevent a cache block from transitioning from a modified state to an exclusive state when the agent invokes the second eviction operation to evict the cache block. In some implementations, the agent may convert from the second eviction operation to the first eviction operation when receiving the second type of eviction message.

公开(公告)号：US12197335B2

公开(公告)日：2025-01-14

申请号：US18182772

申请日：2023-03-13

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Wesley Waylon Terpstra ,  Michael Klinglesmith

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0897

Abstract: Prefetch circuitry may be configured to transmit a message to cancel a prefetch of one or more cache blocks of a group. The message may correspond to a prefetch message by indicating an address for the group and a bit field for the one or more cache blocks of the group to cancel. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.

公开(公告)号：US20240184725A1

公开(公告)日：2024-06-06

申请号：US18497436

申请日：2023-10-30

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F13/18 ,  G06F13/16

CPC classification number: G06F13/18 ,  G06F13/1678 ,  G06F13/1689

Abstract: A data responder may determine a selection between granting a request for a priority byte to be prioritized for transmission ahead of other bytes via a bus and ignoring the request. Granting the request may include transferring a block of bytes of data across multiple clock cycles with the priority byte transferred in a first clock cycle before other clock cycles of the multiple clock cycles. Ignoring the request may include transferring the block across multiple clock cycles with the priority byte transferred in a clock cycle after the first clock cycle. The data responder may receive the request from a data requestor. The data responder may assert a signal on a wire, connected to the data requestor, to indicate a grant of the request and a transfer of the priority byte in the first clock cycle.

公开(公告)号：US11675945B2

公开(公告)日：2023-06-13

申请号：US17734332

申请日：2022-05-02

Applicant: SiFive, Inc.

Inventor： Henry Cook ,  Ernest L. Edgar ,  Ryan Macdonald ,  Wesley Waylon Terpstra

IPC: G06F30/327 ,  G06F30/333 ,  G06F30/3312 ,  G06F30/398 ,  G06F30/3315 ,  G06F30/396 ,  G06F119/12 ,  G06F115/02

CPC classification number: G06F30/327 ,  G06F30/333 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/396 ,  G06F30/398 ,  G06F2115/02 ,  G06F2119/12

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

公开(公告)号：US20230033550A1

公开(公告)日：2023-02-02

申请号：US17961146

申请日：2022-10-06

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook ,  Leigang Kou

IPC: H01S5/042 ,  G01N29/24 ,  H01S5/06 ,  H01S5/10

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

公开(公告)号：US20230004494A1

公开(公告)日：2023-01-05

申请号：US17942283

申请日：2022-09-12

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra

IPC: G06F12/0811 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/0882

Abstract: Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.

公开(公告)号：US20220035987A1

公开(公告)日：2022-02-03

申请号：US17504030

申请日：2021-10-18

Applicant: SiFive, Inc.

Inventor： Megan Wachs ,  Henry Cook ,  Wesley Waylon Terpstra

IPC: G06F30/398 ,  G06F30/333

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

公开(公告)号：US20210011981A1

公开(公告)日：2021-01-14

申请号：US16506507

申请日：2019-07-09

Applicant: SiFive, Inc.

Inventor： Henry Cook ,  Wesley Waylon Terpstra ,  Ryan MacDonald

IPC: G06F17/50 ,  G06F1/08

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

公开(公告)号：US12259825B2

公开(公告)日：2025-03-25

申请号：US18390223

申请日：2023-12-20

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra ,  Richard Van ,  Eric Andrew Gouldey

IPC: G06F12/121 ,  G06F12/0811 ,  G06F12/084

Abstract: Systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. For example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

公开(公告)号：US20240184698A1

公开(公告)日：2024-06-06

申请号：US18341091

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra ,  Eric Andrew Gouldey ,  Michael Klinglesmith ,  Henry Cook

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: A method and apparatus for a cache coherency state request vector is described. A method includes selecting, by a first agent, one or more bits in a cache coherency state request vector, where a selected bit in the cache coherency state request vector indicates an acceptable cache coherency state for a cache block indicated in a request message, transmitting, by the first agent to a second agent, the request message for the cache block, the request message including the cache coherency state request vector, and receiving, by the first agent from the second agent, a response message with a cache coherency response state, wherein the cache coherency response state indicates a cache coherency state responsive to the cache coherency state request vector.