公开(公告)号：US20240303205A1

公开(公告)日：2024-09-12

申请号：US18579134

申请日：2022-06-06

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Yann Loisel ,  John Ingalls ,  Shubhendu Sekhar Mukherjee

IPC: G06F11/07

CPC classification number: G06F11/0787

Abstract: Systems and methods are disclosed for error management in a system on a chip with a securely partitioned memory space. For example, an integrated circuit (e.g., a processor) for executing instructions includes a world identifier checker circuitry configured to check memory requests for one or more memory mapped resources that are received via the bus that have been tagged with a world identifier to determine whether to allow or reject access based on the tagged world identifier; a world identifier checker circuitry configured to compare the tagged world identifier to a world list for a resource that specifies which world identifiers supported by the integrated circuit are authorized for access to the resource; and a data store configured to store world error data, including the tagged world identifier of a memory request that has been rejected by the world identifier checker circuitry.

公开(公告)号：US20230418763A1

公开(公告)日：2023-12-28

申请号：US18203186

申请日：2023-05-30

Applicant: SiFive, Inc.

Inventor： Benoy Alexander ,  John Ingalls ,  Mohit Gopal Wani

IPC: G06F12/1036

CPC classification number: G06F12/1036 ,  G06F2212/681 ,  G06F2212/684

Abstract: Described is a translation lookaside buffer (TLB) prefetcher with multi-level TLB prefetches and feedback architecture. A processing system includes two or more translation lookaside buffer (TLB) levels, each TLB level including a miss queue, and a TLB prefetcher connected to each of the two or more TLB levels. The TLB prefetcher configured to receive feedback from the miss queue at each TLB level for previously sent TLB prefetches and control number of TLB prefetches sent for a trained TLB entry to each TLB level of the two or more TLB levels based on the feedback.

公开(公告)号：US11467961B2

公开(公告)日：2022-10-11

申请号：US17332286

申请日：2021-05-27

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/128

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

公开(公告)号：US11847060B2

公开(公告)日：2023-12-19

申请号：US18115959

申请日：2023-03-01

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Josh Smith

IPC: G06F12/0888 ,  G06F12/0862

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F2212/603 ,  G06F2212/6028

Abstract: Described is a data cache with prediction hints for a cache hit. The data cache includes a plurality of cache lines, where a cache line includes a data field, a tag field, and a prediction hint field. The prediction hint field is configured to store a prediction hint which directs alternate behavior for a cache hit against the cache line. The prediction hint field is integrated with the tag field or is integrated with a way predictor field.

公开(公告)号：US20230205703A1

公开(公告)日：2023-06-29

申请号：US18115959

申请日：2023-03-01

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Josh Smith

IPC: G06F12/0888 ,  G06F12/0862

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F2212/603 ,  G06F2212/6028

Abstract: Described is a data cache with prediction hints for a cache hit. The data cache includes a plurality of cache lines, where a cache line includes a data field, a tag field, and a prediction hint field. The prediction hint field is configured to store a prediction hint which directs alternate behavior for a cache hit against the cache line. The prediction hint field is integrated with the tag field or is integrated with a way predictor field.

公开(公告)号：US20230033550A1

公开(公告)日：2023-02-02

申请号：US17961146

申请日：2022-10-06

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook ,  Leigang Kou

IPC: H01S5/042 ,  G01N29/24 ,  H01S5/06 ,  H01S5/10

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

公开(公告)号：US20210263854A1

公开(公告)日：2021-08-26

申请号：US16797476

申请日：2020-02-21

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Josh Smith

IPC: G06F12/0888

Abstract: Described is a data cache with prediction hints for a cache hit. The data cache includes a plurality of cache lines, where a cache line includes a data field, a tag field, and a prediction hint field. The prediction hint field is configured to store a prediction hint which directs alternate behavior for a cache hit against the cache line. The prediction hint field is integrated with the tag field or is integrated with a way predictor field.

公开(公告)号：US20240338321A1

公开(公告)日：2024-10-10

申请号：US18747414

申请日：2024-06-18

Applicant: SiFive, Inc.

Inventor： John Ingalls

IPC: G06F12/1009 ,  G06F9/30

CPC classification number: G06F12/1009 ,  G06F9/30043 ,  G06F2212/50

Abstract: Systems and methods are disclosed for store-to-load forwarding for processor pipelines. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor pipeline; a store queue that has entries associated with respective store instructions that are being executed, wherein an entry of the store queue includes a tag that is determined based on a virtual address of a target of the associated store instruction; and store-to-load forwarding circuitry that is configured to: compare a first virtual address of a target of a first load instruction being executed by the load unit to respective tags of one or more entries in the store queue; select an entry of the store queue based on a match between the first virtual address and the tag of the selected entry; and forward data of the selected entry in the store queue to be returned by the first load instruction.

公开(公告)号：US20240338219A1

公开(公告)日：2024-10-10

申请号：US18747412

申请日：2024-06-18

Applicant: SiFive, Inc.

Inventor： Paul Walmsley ,  John Ingalls ,  Benoy Alexander

IPC: G06F9/38

CPC classification number: G06F9/3802

Abstract: Disclosed are systems and methods for configuring a prefetcher. A process may reconfigure a prefetcher associated with a processor core responsive to a context switch. The context switch may comprise the processor core changing from executing a first process to a second process. In some implementations, reconfiguring the prefetcher may include updating a register controlling an operation of the prefetcher from a first set of parameters associated with the first process to a second set of parameters associated with the second process. In some implementations, the second set of parameters may be based on input from a process executed in a user mode.

公开(公告)号：US20230029660A1

公开(公告)日：2023-02-02

申请号：US17961137

申请日：2022-10-06

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/0804 ,  G06F12/128

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.