公开(公告)号：US08223573B2

公开(公告)日：2012-07-17

申请号：US12393386

申请日：2009-02-26

申请人： Siegmar Koeppe ,  Martin Ostermayr

发明人： Siegmar Koeppe ,  Martin Ostermayr

IPC分类号： G11C7/14

CPC分类号： G11C8/08 ,  G11C11/417 ,  Y10T29/49002

摘要： Method and device for controlling a memory access and correspondingly configured semiconductor memoryA method and a device for controlling a memory access of a memory comprising memory cells are described. A completion of the memory access is determined by means of at least one dummy bit line. The at least one dummy bit line is connected to a plurality of memory cells of the memory cells of the memory such that a content of the at least one memory cell can be read out via the at least one dummy bit line. The at least one memory cell can be set to a predetermined potential. Each of said plurality of memory cells is connected to the at least one dummy bit line and to at least one dummy word line such that each of said plurality of memory cells can be set to the predetermined potential by means of the at least one dummy bit line and by means of the at least one dummy word line.

摘要翻译： 用于控制存储器访问的方法和设备以及对应配置的半导体存储器描述了一种用于控制包括存储器单元的存储器的存储器访问的方法和设备。 通过至少一个虚拟位线来确定存储器访问的完成。 至少一个虚拟位线连接到存储器的存储器单元的多个存储器单元，使得可以经由至少一个虚拟位线读出至少一个存储单元的内容。 可以将至少一个存储单元设置为预定电位。 所述多个存储器单元中的每一个连接到所述至少一个虚拟位线和至少一个虚拟字线，使得所述多个存储器单元中的每一个可以通过所述至少一个虚拟位被设置为预定电位 并且借助于至少一个虚拟字线。

公开(公告)号：US08209523B2

公开(公告)日：2012-06-26

申请号：US12358048

申请日：2009-01-22

申请人： Ulf Nordqvist ,  Jinan Lin ,  Xiaoning Nie ,  Stefan Maier ,  Siegmar Koeppe

发明人： Ulf Nordqvist ,  Jinan Lin ,  Xiaoning Nie ,  Stefan Maier ,  Siegmar Koeppe

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/325 ,  G06F9/3879

摘要： A data moving processor includes a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.

摘要翻译： 数据移动处理器包括耦合到代码获取电路的代码存储器和耦合到代码提取电路的解码电路。 地址堆栈被耦合到解码电路并被配置为存储地址数据。 通用堆栈耦合到解码电路并且被配置为存储其他数据。 数据移动处理器使用通用堆栈中的数据进行计算。 数据移动处理器使用来自地址堆栈的地址数据来识别源和目的地存储单元。 地址数据可以用于在读或写操作期间驱动存储器的地址线。 使用字节码分别控制地址堆栈和通用堆栈。

公开(公告)号：US20070216451A1

公开(公告)日：2007-09-20

申请号：US11713544

申请日：2007-03-02

申请人： Stephan Henzler ,  Siegmar Koeppe

发明人： Stephan Henzler ,  Siegmar Koeppe

IPC分类号： H03K23/00

CPC分类号： H03K3/356191 ,  H03K3/012 ,  H03K5/00006 ,  H03K5/15013 ,  H03K2005/00286

摘要： A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input. The internal storage nodes of the buffer store elements are either pre-charged at the pre-charge potential or store a logic level, depending on the relevant input clock signals. The differential data inputs of one of the buffer store elements is connected to the internal storage nodes of the other buffer store element and pulsed signals can be tapped off at the internal differential storage node.

摘要翻译： 分频器电路包括至少两个时钟沿控制的差分缓冲器存储器元件，每个元件由互补的输入时钟信号计时，每个时钟信号包括可预充电到预充电电位的内部存储节点，并且每个包括差分数据输入。 缓冲存储器元件的内部存储节点或者是以预充电电位预充电，或根据相关的输入时钟信号存储逻辑电平。 缓冲存储元件之一的差分数据输入连接到另一个缓冲存储元件的内部存储节点，并且脉冲信号可以在内部差分存储节点被分接。

公开(公告)号：US20050163277A1

公开(公告)日：2005-07-28

申请号：US11004047

申请日：2004-12-03

申请人： Georg Georgakos ,  Siegmar Koeppe ,  Thomas Niedermeier

发明人： Georg Georgakos ,  Siegmar Koeppe ,  Thomas Niedermeier

IPC分类号： G11C8/04 ,  G11C19/00 ,  G11C19/28 ,  H03K19/177

CPC分类号： H03K19/17748 ,  G11C8/04 ,  G11C19/00 ,  G11C19/28 ,  H03K19/177

摘要： Shift register for safely providing a configuration bit The invention relates to a shift register cell (1-i, 100-i) for safely providing a configuration bit (6-i) having a master latch (8-i) which can be connected to a serial data input (2-i) on the shift register cell (1-i, 100-i) for the purpose of buffer-storing a data bit (3-i); a first slave latch (10-i) which can be connected to the master latch (8-i) for the purpose of buffer-storing the data bit; at least one second slave latch (12-i) which can be connected to the master latch (8-i) for the purpose of buffer-storing the data bit, and having an evaluation logic unit (13-i) which outputs the configuration bit (6-i) on the basis of the data bits which are buffer-stored in the master latch (8-i) and in the slave latches (10-i, 12-i). In addition, the invention provides a shift register (17) for safely providing configuration bits (6-1, . . . 6-N) which has a plurality of inventive shift register cells (1-1, . . . 1-N, 100-1, . . . 100-N) which are connected in series to form a shift register chain (1, 100).

摘要翻译： 用于安全地提供配置位的移位寄存器技术领域本发明涉及一种用于安全地提供具有主锁存器（8-i）的配置位（6-i）的移位寄存器单元（1-i，100i），其可以连接到 用于缓冲存储数据位（3-i）的移位寄存器单元（1 -i，100-i）上的串行数据输入（2-i）; 第一从锁存器（10-i），其可以连接到主锁存器（8-i），用于缓冲存储数据位; 至少一个第二从锁存器（12-i），其可以连接到主锁存器（8-i），用于缓冲存储数据位，并具有输出配置的评估逻辑单元（13-i） 基于缓冲存储在主锁存器（8-i）和从锁存器（10 -i-12-i）中的数据位来执行位（6-i）。 另外，本发明提供了一种用于安全地提供配置位（6-1，...，6-N）的移位寄存器（17），其具有多个本发明的移位寄存器单元（1至1，...， 100 -1，...，100 -N），其串联连接以形成移位寄存器链（1,100）。