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公开(公告)号：US10892776B1
公开(公告)日：2021-01-12
申请号：US16835939
申请日：2020-03-31
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During each LDPC decoding iterative operation in the decoding phase: the check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit is configured to: determine a syndrome weight according to the syndrome from the check-node circuit; obtain a previous codeword from a variable-node memory without obtaining a channel value from a channel-value memory; perform bit-flipping on one or more codeword bits in the previous codeword according to the calculated syndrome weight to generate an updated codeword; and subtract the previous codeword from the updated codeword to obtain the codeword difference.
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公开(公告)号：US20200117591A1
公开(公告)日：2020-04-16
申请号：US16273093
申请日：2019-02-11
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: An encoder of a flash memory controller is provided, which includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. The barrel shifter module processes multiple data blocks to generate multiple partial parity blocks including a first portion, a second portion and a third portion. The inverse matrix calculating circuit performs inverse matrix calculating operations on the first portion to generate a first portion of parity blocks. The calculating circuit performs inverse matrix calculating operations on the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity blocks. The first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity blocks serve as multiple parity blocks generated in response to encoding the data blocks.
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公开(公告)号：US10523243B2
公开(公告)日：2019-12-31
申请号：US16038147
申请日：2018-07-17
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.
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公开(公告)号：US20190158115A1
公开(公告)日：2019-05-23
申请号：US15820391
申请日：2017-11-21
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.
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