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公开(公告)号：US11901912B1
公开(公告)日：2024-02-13
申请号：US17933195
申请日：2022-09-19
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo , Zhen-U Liu
CPC classification number: H03M13/1128 , H03M13/1111 , H03M13/1575
Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.
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2.发明授权公开(公告)号：US10938417B2
公开(公告)日：2021-03-02
申请号：US16558146
申请日：2019-09-01
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: The present invention provides an encoding circuit of a flash memory controller, wherein the encoding circuit includes an auxiliary data generating circuit and an encoder. In the operations of the encoding circuit, the auxiliary data generating circuit is configured to receive a plurality of data chunks to generate auxiliary data corresponding to the data chunks. The encoder is configured to encode the data blocks to generate parity codes according to a parity check matrix, and to use the auxiliary data to replace a portion of the parity codes to generate adjusted parity codes, wherein the data chunks and the adjusted parity codes are written into a flash.
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公开(公告)号：US12149260B2
公开(公告)日：2024-11-19
申请号：US18143343
申请日：2023-05-04
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo , Hung-Jen Huang
Abstract: A method and apparatus for decoding a Low-Density Parity-Check (LDPC) code whereby the apparatus comprises an LDPC decoder comprising variable-node calculation circuitry and check-node calculation circuitry: the check-node calculation circuitry is arranged operably to perform a modulo 2 multiplication on a codeword and a parity check matrix to calculate a plurality of first syndromes in a first-stage state. The variable-node calculation circuitry is arranged operably to perform a bit flipping algorithm to generate variable nodes, and calculate soft bits for the variable nodes in a second-stage state. The check-node calculation circuitry is arranged to perform the modulo 2 multiplication on the variable nodes and the parity check matrix to calculate second syndromes in the second-stage. When second syndromes indicate that the previously generated variable nodes are incorrect, a third stage state is repeated until decoding succeeds or a total number of iterations exceeds a threshold.
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公开(公告)号：US11876535B1
公开(公告)日：2024-01-16
申请号：US17933190
申请日：2022-09-19
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
CPC classification number: H03M13/1111 , H03M13/1128 , H03M13/1575
Abstract: A memory controller, for use in a data storage device, is provided. A low-density parity-check (LDPC) decoding procedure performed by the memory controller includes an initial phase, a decoding phase, and an output phase in sequence. The memory controller includes a memory-index control circuit and a decoder. The decoder includes a decoding pipeline to perform the decoding phase of the LDPC decoding procedure. After the data storage device is booted up, the decoder reads a plurality of first codewords from a variable-node memory using a first order via the memory-index control circuit for LDPC decoding. In response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding. The first order is different from the second order.
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公开(公告)号：US11115063B2
公开(公告)日：2021-09-07
申请号：US16835863
申请日：2020-03-31
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A flash memory controller is configured to decode a codeword. During the decoding process, the flash memory can check the decoding status of each codeword segment in the codeword and skip the decoding of a codeword segment whose decoding status is passed, thereby saving time decoding and also improving decoding efficiency. Even though only a part of the codeword segments in the codeword have been successfully decoded in the decoding process at the previous time, the flash memory controller can replace the part of the codeword segments in the codeword with the correct results obtained previously, and then decoding the re-formed codeword again. Accordingly, the decoding accuracy can be increased and the burden on the subsequent decoding process or data recovery can be reduced.
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Patent Agency Ranking
公开(公告)号：US11296725B2
公开(公告)日：2022-04-05
申请号：US16726808
申请日：2019-12-24
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.
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公开(公告)号：US11108408B2
公开(公告)日：2021-08-31
申请号：US16835906
申请日：2020-03-31
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit is configured to obtain a codeword difference from the variable-node circuit, and calculate a syndrome according to the codeword difference. During each LDPC (low-density parity check) decoding iterative operation, the variable-node circuit executes the following steps: determining syndrome weight according to a channel value and the syndrome from the check-node circuit; obtaining a previous codeword generated by a previous LDPC decoding iterative operation; determining a flipping strategy of a bit-flipping algorithm for each codeword bit in the previous codeword according to the syndrome weight and a predetermined threshold, and flipping one or more codeword bits in the previous codeword according to the flipping strategy to generate an updated codeword; and subtracting the previous codeword from the updated codeword to generate the codeword difference.
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公开(公告)号：US20200091939A1
公开(公告)日：2020-03-19
申请号：US16691552
申请日：2019-11-21
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.
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公开(公告)号：US10523236B2
公开(公告)日：2019-12-31
申请号：US15820391
申请日：2017-11-21
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.
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公开(公告)号：US20190165817A1
公开(公告)日：2019-05-30
申请号：US16038147
申请日：2018-07-17
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.
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