公开(公告)号：US08942333B2

公开(公告)日：2015-01-27

申请号：US13674154

申请日：2012-11-12

Applicant: Texas Instruments Incorporated

Inventor： Arvind Kumar ,  Shobhit Singhal ,  Vikas Lakhanpal ,  Kalpesh Amrutlal Shah

IPC: H04L7/00 ,  H04L7/02

CPC classification number: H04L7/0037 ,  G01R25/04 ,  H03L7/0814 ,  H04L7/0012 ,  H04L7/0045

Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.

Abstract translation: 用于相位对准由相应的第一和第二电路系统使用的至少两个时钟的装置和方法，例如芯片系统上的系统中的存储器控​​制器和DDR PHY接口。 第一电路对第一电路系统使用的第一时钟的相位进行采样，然后延迟电路选择性地延迟第二电路系统使用的第二时钟并设置第二时钟的延迟定时。 为了节省资源并减少芯片面积，逻辑电路接收第一时钟的采样相位，确定哪个延迟定时与采样相位的时序相匹配，并将延迟电路设置为对应于与采样相关的延迟定时相对应的固定延迟定时 相。 因此，通过较少的资源实现两个时钟的相位对准。

公开(公告)号：US20140133613A1

公开(公告)日：2014-05-15

申请号：US13674154

申请日：2012-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arvind Kumar ,  Shobhit Singhal ,  Vikas Lakhanpal ,  Kalpesh Amrutlal Shah

IPC: H04L7/02

CPC classification number: H04L7/0037 ,  G01R25/04 ,  H03L7/0814 ,  H04L7/0012 ,  H04L7/0045

Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.

Abstract translation: 用于相位对准由相应的第一和第二电路系统使用的至少两个时钟的装置和方法，例如芯片系统上的系统中的存储器控​​制器和DDR PHY接口。 第一电路对第一电路系统使用的第一时钟的相位进行采样，然后延迟电路选择性地延迟第二电路系统使用的第二时钟并设置第二时钟的延迟定时。 为了节省资源并减少芯片面积，逻辑电路接收第一时钟的采样相位，确定哪个延迟定时与采样相位的时序相匹配，并将延迟电路设置为对应于与采样相关的延迟定时相对应的固定延迟定时 相。 因此，通过较少的资源实现两个时钟的相位对准。