公开(公告)号：US08942333B2

公开(公告)日：2015-01-27

申请号：US13674154

申请日：2012-11-12

Applicant: Texas Instruments Incorporated

Inventor： Arvind Kumar ,  Shobhit Singhal ,  Vikas Lakhanpal ,  Kalpesh Amrutlal Shah

IPC: H04L7/00 ,  H04L7/02

CPC classification number: H04L7/0037 ,  G01R25/04 ,  H03L7/0814 ,  H04L7/0012 ,  H04L7/0045

Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.

Abstract translation: 用于相位对准由相应的第一和第二电路系统使用的至少两个时钟的装置和方法，例如芯片系统上的系统中的存储器控​​制器和DDR PHY接口。 第一电路对第一电路系统使用的第一时钟的相位进行采样，然后延迟电路选择性地延迟第二电路系统使用的第二时钟并设置第二时钟的延迟定时。 为了节省资源并减少芯片面积，逻辑电路接收第一时钟的采样相位，确定哪个延迟定时与采样相位的时序相匹配，并将延迟电路设置为对应于与采样相关的延迟定时相对应的固定延迟定时 相。 因此，通过较少的资源实现两个时钟的相位对准。

公开(公告)号：US20140133613A1

公开(公告)日：2014-05-15

申请号：US13674154

申请日：2012-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arvind Kumar ,  Shobhit Singhal ,  Vikas Lakhanpal ,  Kalpesh Amrutlal Shah

IPC: H04L7/02

CPC classification number: H04L7/0037 ,  G01R25/04 ,  H03L7/0814 ,  H04L7/0012 ,  H04L7/0045

Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.

Abstract translation: 用于相位对准由相应的第一和第二电路系统使用的至少两个时钟的装置和方法，例如芯片系统上的系统中的存储器控​​制器和DDR PHY接口。 第一电路对第一电路系统使用的第一时钟的相位进行采样，然后延迟电路选择性地延迟第二电路系统使用的第二时钟并设置第二时钟的延迟定时。 为了节省资源并减少芯片面积，逻辑电路接收第一时钟的采样相位，确定哪个延迟定时与采样相位的时序相匹配，并将延迟电路设置为对应于与采样相关的延迟定时相对应的固定延迟定时 相。 因此，通过较少的资源实现两个时钟的相位对准。

公开(公告)号：US08890588B2

公开(公告)日：2014-11-18

申请号：US13852326

申请日：2013-03-28

Applicant: Texas Instruments Incorporated

Inventor： Kalpesh Amrutlal Shah ,  Arvind Kumar ,  Francisco Adolfo Cano

IPC: H03L7/00 ,  H03L7/24

CPC classification number: G06F1/24 ,  G06F1/04 ,  G06F1/06

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract translation: 在一个实施例中，在集成电路（IC）中配置用于非对称衰减防止的电路包括主时钟，其被配置为产生主时钟信号，辅时钟被配置为产生辅时钟信号，状态确定电路和控制电路 。 状态确定电路被配置为确定与IC中的主时钟条件和上电复位状态中的至少一个相关联的当前工作状态。 控制电路被配置为响应于第一操作状态的确定而产生控制信号。 控制信号被配置为在确定第一操作状态时促进从主时钟到次时钟的转换，以及在确定第二操作状态时从安全操作模式转换到正常操作模式。 次级时钟与IC的安全工作模式相关联。

公开(公告)号：US20140292383A1

公开(公告)日：2014-10-02

申请号：US13852326

申请日：2013-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kalpesh Amrutlal Shah ,  Arvind Kumar ,  Francisco Adolfo Cano

IPC: H03L7/24

CPC classification number: G06F1/24 ,  G06F1/04 ,  G06F1/06

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract translation: 在一个实施例中，在集成电路（IC）中配置用于非对称衰减防止的电路包括主时钟，其被配置为产生主时钟信号，辅时钟被配置为产生辅时钟信号，状态确定电路和控制电路 。 状态确定电路被配置为确定与IC中的主时钟条件和上电复位状态中的至少一个相关联的当前工作状态。 控制电路被配置为响应于第一操作状态的确定而产生控制信号。 控制信号被配置为在确定第一操作状态时促进从主时钟到次时钟的转换，以及在确定第二操作状态时从安全操作模式转换到正常操作模式。 次级时钟与IC的安全工作模式相关联。