公开(公告)号：US20220359504A1

公开(公告)日：2022-11-10

申请号：US17869069

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L27/088 ,  H01L29/786 ,  H01L29/423

摘要： A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes first channel members between a first and a second source/drain feature, a first gate structure wrapping around the first channel members, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. The second transistor includes second channel members between a third and a fourth source/drain features, a second gate structure wrapping around the second channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. A distance between the second gate spacer and the second source/drain contact is greater than a distance between the first gate spacer and the first source/drain contact.

公开(公告)号：US20220343972A1

公开(公告)日：2022-10-27

申请号：US17858376

申请日：2022-07-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： G11C11/419 ,  G11C11/412

摘要： An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit.

公开(公告)号：US20220328362A1

公开(公告)日：2022-10-13

申请号：US17843727

申请日：2022-06-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08

摘要： Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

公开(公告)号：US11411090B2

公开(公告)日：2022-08-09

申请号：US16550797

申请日：2019-08-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/78

摘要： Gate-all-around (GAA) device and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) device comprises a first nanostructure and a second nanostructure formed on a substrate, wherein each of the first nano structure and the second nanostructure includes a plurality of semiconductor layers and each of the first nanostructure and the second nanostructure includes a channel region and a source/drain (S/D) region; a first gate structure wrapping the plurality of semiconductor layers of the first nanostructure and a second gate structure wrapping the plurality of semiconductor layers of the second nanostructure; and a S/D contact that contacts at least one of the plurality of semiconductor layers of the first nanostructure and at least one of the plurality of semiconductor layers of the second nanostructure.

公开(公告)号：US11367663B2

公开(公告)日：2022-06-21

申请号：US17120563

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08

摘要： Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

公开(公告)号：US20220189956A1

公开(公告)日：2022-06-16

申请号：US17688146

申请日：2022-03-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L27/02

摘要： A semiconductor device includes a substrate; semiconductor fins over the substrate and oriented lengthwise along a first direction; first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein the first and the second MDL fins are intermixed with the semiconductor fins, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer and the inner dielectric layer have different dielectric materials; and gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage the semiconductor fins and the second MDL fins.

公开(公告)号：US11277136B2

公开(公告)日：2022-03-15

申请号：US16948042

申请日：2020-08-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H03K19/1776 ,  H01L27/105 ,  H03K19/20

摘要： Structures and methods for the co-optimization of core (logic) devices and SRAM devices include a semiconductor device having a logic portion and a memory portion. In some embodiments, a logic device is disposed within the logic portion. In some cases, the logic device includes a single fin N-type FinFET and a single fin P-type FinFET. In some examples, a static random-access memory (SRAM) device is disposed within the memory portion. The SRAM device includes an N-well region disposed between two P-well regions, where the two P-well regions include an N-type FinFET pass gate (PG) transistor and an N-type FinFET pull-down (PD) transistor, and where the N-well region includes a P-type FinFET pull-up (PU) transistor.

公开(公告)号：US20210408262A1

公开(公告)日：2021-12-30

申请号：US17475009

申请日：2021-09-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238

摘要： The present disclosure provides a semiconductor device and a method of forming the same. In an embodiment, the semiconductor device includes a fin extending from a substrate, a gate structure over the channel region, a first spacer extending along a sidewall of the lower portion of the gate structure, and a second spacer extending along a sidewall of the upper portion of the gate structure. The fin includes a channel region and a source/drain (S/D) region adjacent to the channel region. The gate structure includes an upper portion and a lower portion. The second spacer is disposed on a top surface of the first spacer. The first spacer is formed of a first dielectric material and the second spacer is formed of a second dielectric material different from the first dielectric material.

公开(公告)号：US20210375355A1

公开(公告)日：2021-12-02

申请号：US16888509

申请日：2020-05-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Dian-Sheg Yu ,  Jhon Jhy Liaw ,  Ren-Fen Tsui ,  Bing-Chian Lin

IPC分类号： G11C11/418 ,  H01L27/11 ,  H01L23/528 ,  G11C11/419

摘要： A memory device includes a plurality of memory cells located in a first region of the memory device. The memory cells include a first signal line, a first circuit located in the first region of the memory device, and a plurality of logic circuits located in a second region of the memory device. The second region and the first region have different design rules. The first circuit is configured to be selectively enabled and disabled. When the first circuit is enabled, the first signal line is electrically coupled in parallel with a second signal line.

公开(公告)号：US11121234B2

公开(公告)日：2021-09-14

申请号：US16392769

申请日：2019-04-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

摘要： The present disclosure provides a semiconductor device and a method of forming the same. In an embodiment, the semiconductor device includes a fin extending from a substrate, a gate structure over the channel region, a first spacer extending along a sidewall of the lower portion of the gate structure, and a second spacer extending along a sidewall of the upper portion of the gate structure. The fin includes a channel region and a source/drain (S/D) region adjacent to the channel region. The gate structure includes an upper portion and a lower portion. The second spacer is disposed on a top surface of the first spacer. The first spacer is formed of a first dielectric material and the second spacer is formed of a second dielectric material different from the first dielectric material.