公开(公告)号：US20180151707A1

公开(公告)日：2018-05-31

申请号：US15648201

申请日：2017-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng WU ,  Li-Feng TENG

IPC: H01L29/66 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11531 ,  H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11546 ,  H01L27/11548 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/788

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.