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公开(公告)号:US20190189633A1
公开(公告)日:2019-06-20
申请号:US16284948
申请日:2019-02-25
申请人: SK hynix Inc.
发明人: Kang Sik CHOI , Bong Hoon LEE , Seung Cheol LEE
IPC分类号: H01L27/11582 , G11C5/06 , H01L29/66 , H01L29/788 , H01L29/423 , H01L27/11556 , G11C16/04 , H01L27/11521
CPC分类号: H01L27/11582 , G11C5/063 , G11C16/0483 , H01L27/11521 , H01L27/11556 , H01L29/42328 , H01L29/66825 , H01L29/66833 , H01L29/788
摘要: A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.
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公开(公告)号:US20190013322A1
公开(公告)日:2019-01-10
申请号:US15677033
申请日:2017-08-15
发明人: Yi-Tsung Tsai , Yu-Chun Yang , Fang-Wei Lin , Hsin-Li Kuo
IPC分类号: H01L27/11521 , H01L23/29 , H01L29/423 , H01L23/31 , H01L23/535 , H01L29/66 , H01L21/768 , H01L29/788
CPC分类号: H01L27/11521 , H01L21/0217 , H01L21/31116 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/291 , H01L23/3171 , H01L23/3192 , H01L23/535 , H01L29/40114 , H01L29/42324 , H01L29/6656 , H01L29/66825 , H01L29/788
摘要: A memory structure including a substrate, a memory cell structure, and a protective layer structure is provided. The memory cell structure is disposed on the substrate and has a first side and a second side opposite to each other. The protective layer structure covers the memory cell structure. The material of the protective layer structure is nitride. The protective layer structure is a continuous structure. The height of the protective layer structure adjacent to the second side of the memory cell structure is greater than the height of the protective layer structure adjacent to the first side of the memory cell structure.
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公开(公告)号:US20180261558A1
公开(公告)日:2018-09-13
申请号:US15976077
申请日:2018-05-10
申请人: Verisiti, LLC
IPC分类号: H01L23/00 , H01L23/528 , H01L27/11524 , H01L29/788
CPC分类号: H01L23/573 , H01L23/5223 , H01L23/5228 , H01L23/528 , H01L27/0203 , H01L27/0629 , H01L27/11517 , H01L27/11524 , H01L28/24 , H01L28/60 , H01L29/788 , H01L2924/0002 , H01L2924/00
摘要: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
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公开(公告)号:US10056493B2
公开(公告)日:2018-08-21
申请号:US15853875
申请日:2017-12-25
发明人: Zhibiao Zhou , Ding-Lung Chen , Chen-Bin Lin , Sanpo Wang , Chung-Yuan Lee , Chi-Fa Ku
IPC分类号: H01L29/78 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号: H01L29/78609 , H01L29/42328 , H01L29/42344 , H01L29/78648 , H01L29/7869 , H01L29/788 , H01L29/7881 , H01L29/792
摘要: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.
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公开(公告)号:US10038101B2
公开(公告)日:2018-07-31
申请号:US15515199
申请日:2015-10-06
申请人: Floadia Corporation
发明人: Yutaka Shinagawa , Yasuhiro Taniguchi , Hideo Kasai , Ryotaro Sakurai , Yasuhiko Kawashima , Tatsuro Toya , Kosuke Okuyama
IPC分类号: H01L29/788 , H01L29/792 , H01L45/00 , G11C11/34
CPC分类号: H01L29/788 , G11C11/34 , G11C16/0425 , G11C16/0433 , G11C16/08 , H01L27/115 , H01L28/00 , H01L29/792 , H01L45/04
摘要: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.
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公开(公告)号:US10037888B2
公开(公告)日:2018-07-31
申请号:US15093933
申请日:2016-04-08
发明人: Byoungkeun Son , Hansoo Kim , Jinho Kim , Kihyun Kim
IPC分类号: H01L29/788 , H01L21/28 , H01L29/66 , H01L29/423 , H01L29/78 , H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11553 , H01L27/11519
CPC分类号: H01L21/28 , H01L27/11519 , H01L27/11551 , H01L27/11553 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/42364 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/7841 , H01L29/788 , H01L29/7883 , H01L29/7889
摘要: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.
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公开(公告)号:US20180212141A1
公开(公告)日:2018-07-26
申请号:US15877806
申请日:2018-01-23
发明人: Nishtha Sharma , Peter Dowben , Andrew Marshall
CPC分类号: H01L43/02 , G11C11/005 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/22 , G11C16/0416 , G11C16/0441 , H01F10/3254 , H01L29/78391 , H01L29/788 , H01L43/08 , H01L45/08
摘要: A magneto-electric magnetic tunnel junction device (ME-MTJ) that permits direct driving of ME-MTJ devices by a prior ME-MTJ device is the unipolar magneto-electric magnetic tunnel junction (UMMTJ) device. The UMMTJ device enables full logic circuitry to be implemented without level shifting between each logic element.
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公开(公告)号:US20180211965A1
公开(公告)日:2018-07-26
申请号:US15744163
申请日:2016-07-21
申请人: FLOADIA CORPORATION
发明人: Shoji YOSHIDA , Fukuo OWADA , Daisuke OKADA , Yasuhiko KAWASHIMA , Shinji YOSHIDA , Kazumasa YANAGISAWA , Yasuhiro TANIGUCHI
IPC分类号: H01L27/115 , H01L29/788 , H01L29/792 , H01L21/28
CPC分类号: H01L27/115 , H01L21/28 , H01L27/10 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/40117 , H01L29/42344 , H01L29/66833 , H01L29/788 , H01L29/792
摘要: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
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公开(公告)号:US10026836B2
公开(公告)日:2018-07-17
申请号:US15431158
申请日:2017-02-13
IPC分类号: H01L29/78 , H01L29/423 , H01L29/51 , H01L29/788 , H01L27/11521 , H01L29/49 , H01L21/28 , H01L29/66 , H01L27/1159 , H01L27/11597
CPC分类号: H01L29/78391 , H01L27/11521 , H01L27/1159 , H01L27/11597 , H01L29/40111 , H01L29/42336 , H01L29/4236 , H01L29/495 , H01L29/51 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/518 , H01L29/6684 , H01L29/788
摘要: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.
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公开(公告)号:US20180197887A1
公开(公告)日:2018-07-12
申请号:US15117887
申请日:2016-07-20
发明人: Yang LIU
IPC分类号: H01L27/12 , H01L29/24 , H01L29/786 , H01L29/788
CPC分类号: H01L27/1225 , H01L21/77 , H01L27/12 , H01L27/127 , H01L27/15 , H01L29/24 , H01L29/78648 , H01L29/7869 , H01L29/788
摘要: The present disclosure discloses an array substrate, the array substrate comprises a substrate as well as a thin film transistor and a pixel electrode formed on the substrate, wherein the top of the thin film transistor is formed a floating gate electrode, at least portion of the floating gate electrode and the pixel electrode are made of the same material. The present disclosure also discloses a manufacturing method of an array substrate. Through this way, the present disclosure simultaneously forms a floating gate electrode in the manufacturing process of the pixel electrode, the pixel electrode and the floating gate electrode is formed by a mask, there is no need to add a mask, thus achieving the manufacture of the dual gate thin film transistor and the array substrate, briefing the process, reducing the production costs.
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