公开(公告)号：US11183449B1

公开(公告)日：2021-11-23

申请号：US16881005

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Jin Cai ,  Yu-Sheng Chen

IPC: H01L23/50 ,  H01L21/82 ,  H01L23/44 ,  H01L23/367 ,  H01L23/427 ,  H01L23/433

Abstract: Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processor, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processor is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processor. The buffer device is disposed on the data processor. The thermally conductive shield covers the data processor, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processor.

公开(公告)号：US11152565B2

公开(公告)日：2021-10-19

申请号：US16573615

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Sheng Chen ,  Da-Ching Chiou ,  Jau-Yi Wu ,  Carlos H. Diaz

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device includes a conductive wire, a first 2-D material layer, a phase change element, and a top electrode. The first 2-D material layer is over the conductive wire. The phase change element extends along a surface of the first 2-D material layer distal to the conductive layer. The top electrode is over the phase change element.

公开(公告)号：US20200343446A1

公开(公告)日：2020-10-29

申请号：US16394177

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present disclosure are directed towards a resistive random access memory (RRAM) device including a scavenger layer. A bit line overlying a semiconductor substrate. A data storage layer around outer sidewalls and a top surface of the bit line. A word line overlying the data storage layer. A scavenger layer between the word line and the bit line such that a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line. A lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer.

公开(公告)号：US10541365B1

公开(公告)日：2020-01-21

申请号：US15998689

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Jau-Yi Wu ,  Yu-Sheng Chen ,  Carlos H. Diaz

IPC: H01L45/00 ,  H01L27/24

Abstract: The current disclosure describes techniques for patterning a phase-change memory layer. A SiON layer is used as a first hard mask and an electrical conductive protective layer is used as a second hard mask to pattern the phase-change memory layer. An organic BARC layer is sued to improve the photolithography accuracy. The thickness ratio between the organic BARC layer and the hard mask SiON layer and the etching conditions of the hard mask SiON layer are controlled such that the patterned organic BARC layer is completely or near completely resolved simultaneously with the patterning of the hard mask SiON layer.