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公开(公告)号：US11837611B2
公开(公告)日：2023-12-05
申请号：US17000582
申请日：2020-08-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Li Chiang , Chao-Ching Cheng , Jung-Piao Chiu , Tzu-Chiang Chen , Yu-Sheng Chen
IPC: H01L45/00 , H01L27/146 , H10N70/00
CPC classification number: H01L27/146 , H10N70/021 , H10N70/841
Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.
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公开(公告)号：US20210035633A1
公开(公告)日：2021-02-04
申请号：US16805872
申请日：2020-03-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Li Chiang , Chao-Ching Cheng , Tzu-Chiang Chen , Yu-Sheng Chen , Hon-Sum Philip Wong
Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.
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公开(公告)号：US10862031B2
公开(公告)日：2020-12-08
申请号：US16289733
申请日：2019-03-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu Chao Lin , Jui-Ming Chen , Shao-Ming Yu , Tung Ying Lee , Yu-Sheng Chen
Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.
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公开(公告)号：US11862243B2
公开(公告)日：2024-01-02
申请号：US17876379
申请日：2022-07-28
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jau-Yi Wu , Win-San Khwa , Jin Cai , Yu-Sheng Chen
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C2013/0052 , G11C2013/0054
Abstract: A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value. A memory device is also disclosed herein.
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公开(公告)号：US11183236B2
公开(公告)日：2021-11-23
申请号：US16805872
申请日：2020-03-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Li Chiang , Chao-Ching Cheng , Tzu-Chiang Chen , Yu-Sheng Chen , Hon-Sum Philip Wong
Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.
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Patent Agency Ranking
公开(公告)号：US11139431B2
公开(公告)日：2021-10-05
申请号：US16394177
申请日：2019-04-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Li Chiang , Chao-Ching Cheng , Tzu-Chiang Chen , Yu-Sheng Chen
Abstract: Various embodiments of the present disclosure are directed towards a resistive random access memory (RRAM) device including a scavenger layer. A bit line overlying a semiconductor substrate. A data storage layer around outer sidewalls and a top surface of the bit line. A word line overlying the data storage layer. A scavenger layer between the word line and the bit line such that a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line. A lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer.
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公开(公告)号：US10818349B2
公开(公告)日：2020-10-27
申请号：US16406897
申请日：2019-05-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jau-Yi Wu , Yu-Sheng Chen
Abstract: Methods for programming or reading a memory cell are disclosed. The methods include following operations. A read voltage at a first read voltage level is applied to read a memory cell for detecting a resistance level of the memory cell. The read voltage at a second read voltage level, different from the first read voltage level, is applied to read the memory cell for determining a waveform type has been utilized to program the memory cell. The resistance level and the waveform type are combined to recognize data bits stored in the memory cell.
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公开(公告)号：US20200279998A1
公开(公告)日：2020-09-03
申请号：US16289733
申请日：2019-03-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu Chao Lin , Jui-Ming Chen , Shao-Ming Yu , Tung Ying Lee , Yu-Sheng Chen
Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.
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公开(公告)号：US11588106B2
公开(公告)日：2023-02-21
申请号：US17081159
申请日：2020-10-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu Chao Lin , Jui-Ming Chen , Shao-Ming Yu , Tung Ying Lee , Yu-Sheng Chen
Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.
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公开(公告)号：US11443803B2
公开(公告)日：2022-09-13
申请号：US17095664
申请日：2020-11-11
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jau-Yi Wu , Win-San Khwa , Jin Cai , Yu-Sheng Chen
IPC: G11C13/00
Abstract: A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.
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