公开(公告)号：US07711899B2

公开(公告)日：2010-05-04

申请号：US11169858

申请日：2005-06-30

申请人： Takaharu Ishizuka ,  Daisuke Itou ,  Takashi Yamamoto

发明人： Takaharu Ishizuka ,  Daisuke Itou ,  Takashi Yamamoto

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0822

摘要： An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temporarily the data read by the plurality of processing units from respective main memories in combination with tag information indicating the state of the data that will be stored, and a system controller for controlling the access of the plurality of processing units to the main memories. The system controller comprises a tag copy unit for holding a copy of the tag information that will be stored in the cache memory, a plurality of write cues for storing write requests, and a store buffer for storing the arbitration results relating to a plurality of write requests that will be stored in the plurality of write cues.

摘要翻译： 多处理器配置的信息处理设备可以显着增加读请求的处理能力。 信息处理装置包括多个处理单元，多个高速缓冲存储器，用于暂时存储来自各个主存储器的多个处理单元读取的数据与表示将被存储的数据的状态的标签信息，以及 系统控制器，用于控制多个处理单元对主存储器的访问。 系统控制器包括用于保存将被存储在高速缓冲存储器中的标签信息的副本的标签复制单元，用于存储写请求的多个写入提示，以及用于存储与多个写入有关的仲裁结果的存储缓冲器 将存储在多个写入提示中的请求。

公开(公告)号：US07694106B2

公开(公告)日：2010-04-06

申请号：US11785891

申请日：2007-04-20

申请人： Toshikazu Ueki ,  Takaharu Ishizuka ,  Makoto Hataida ,  Takashi Yamamoto ,  Yuka Hosokawa ,  Takeshi Owaki ,  Daisuke Itou

发明人： Toshikazu Ueki ,  Takaharu Ishizuka ,  Makoto Hataida ,  Takashi Yamamoto ,  Yuka Hosokawa ,  Takeshi Owaki ,  Daisuke Itou

IPC分类号： G06F9/00

CPC分类号： G06F12/0813 ,  G06F12/1072

摘要： A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.

摘要翻译： 多处理器系统包括判断单元，判断单元判断输入到全局地址交叉开关的读取命令是否是对自身系统板上的存储器的读取命令，当判断单元判断读取命令是读取命令时，执行单元推测执行 基于从全局地址交叉开关通知的地址，在全局访问之前的读取命令，在CPU上提供的数据队列中从存储器读取数据的设置单元设置，而不排队数据 设置在存储器上的数据队列，以及指示单元，根据来自全局地址交叉开关的通知指示CPU上提供的数据队列，丢弃数据或将数据发送到CPU。

公开(公告)号：US20080046694A1

公开(公告)日：2008-02-21

申请号：US11785891

申请日：2007-04-20

申请人： Toshikazu Ueki ,  Takaharu Ishizuka ,  Makoto Hataida ,  Takashi Yamamoto ,  Yuka Hosokawa ,  Takeshi Owaki ,  Daisuke Itou

发明人： Toshikazu Ueki ,  Takaharu Ishizuka ,  Makoto Hataida ,  Takashi Yamamoto ,  Yuka Hosokawa ,  Takeshi Owaki ,  Daisuke Itou

IPC分类号： G06F9/30

CPC分类号： G06F12/0813 ,  G06F12/1072

摘要： A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.

摘要翻译： 多处理器系统包括判断单元，判断单元判断输入到全局地址交叉开关的读取命令是否是对自身系统板上的存储器的读取命令，当判断单元判断读取命令是读取命令时，执行单元推测执行 基于从全局地址交叉开关通知的地址，在全局访问之前的读取命令，在CPU上提供的数据队列中从存储器读取数据的设置单元设置，而不排队数据 设置在存储器上的数据队列，以及指示单元，根据来自全局地址交叉开关的通知指示CPU上提供的数据队列，丢弃数据或将数据发送到CPU。

公开(公告)号：US20060212652A1

公开(公告)日：2006-09-21

申请号：US11169858

申请日：2005-06-30

申请人： Takaharu Ishizuka ,  Daisuke Itou ,  Takashi Yamamoto

发明人： Takaharu Ishizuka ,  Daisuke Itou ,  Takashi Yamamoto

IPC分类号： G06F12/00 ,  G06F13/28

CPC分类号： G06F12/0822

摘要： An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temporarily the data read by the plurality of processing units from respective main memories in combination with tag information indicating the state of the data that will be stored, and a system controller for controlling the access of the plurality of processing units to the main memories. The system controller comprises a tag copy unit for holding a copy of the tag information that will be stored in the cache memory, a plurality of write cues for storing write requests, and a store buffer for storing the arbitration results relating to a plurality of write requests that will be stored in the plurality of write cues.

摘要翻译： 多处理器配置的信息处理设备可以显着增加读请求的处理能力。 信息处理装置包括多个处理单元，多个高速缓存存储器，用于暂时存储来自各个主存储器的多个处理单元读取的数据与表示将被存储的数据的状态的标签信息，以及 系统控制器，用于控制多个处理单元对主存储器的访问。 系统控制器包括用于保存将被存储在高速缓冲存储器中的标签信息的副本的标签复制单元，用于存储写入请求的多个写入提示，以及用于存储与多个写入有关的仲裁结果的存储缓冲器 将存储在多个写入提示中的请求。

公开(公告)号：US20100191942A1

公开(公告)日：2010-07-29

申请号：US12659896

申请日：2010-03-24

申请人： Takeshi Owaki ,  Takaharu Ishizuka ,  Toshikazu Ueki ,  Makoto Hataida ,  Yuka Hosokawa ,  Atsushi Morosawa ,  Takashi Yamamoto ,  Daisuke Itou

发明人： Takeshi Owaki ,  Takaharu Ishizuka ,  Toshikazu Ueki ,  Makoto Hataida ,  Yuka Hosokawa ,  Atsushi Morosawa ,  Takashi Yamamoto ,  Daisuke Itou

IPC分类号： G06F9/30

CPC分类号： G06F11/1658 ,  G06F11/165 ,  G06F11/1679 ,  G06F2201/81

摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.

摘要翻译： 北桥在检测到冗余CPU的同步中断时，停止发生错误的异常CPU总线的运行，FWH中的固件指示北桥禁止外部指令。 此外，固件还保存连接到普通CPU总线的正常CPU的内部信息，并将存储器上的数据缓存，并将北桥问题重置到家庭系统板中的所有CPU。 然后，固件将CPU的内部信息恢复到所有CPU的存储器上，并指示北桥取消对外部指令的禁止。

公开(公告)号：US20100060177A1

公开(公告)日：2010-03-11

申请号：US12553361

申请日：2009-09-03

申请人： Go TAKATA ,  Shinichiro Kataoka ,  Yasunori Yamamoto ,  Tsukasa Kawahara ,  Ryuji Ueda ,  Daisuke Itou

发明人： Go TAKATA ,  Shinichiro Kataoka ,  Yasunori Yamamoto ,  Tsukasa Kawahara ,  Ryuji Ueda ,  Daisuke Itou

IPC分类号： H05B37/02 ,  G05F1/00

CPC分类号： H05B33/0815 ,  H05B33/0824

摘要： The load driving apparatus according to the present invention includes a load current setting signal generating section, a load current generating section, a reference voltage generating section and a drive voltage generating section. The load current setting signal generating section generates a desired load current setting signal. The load current generating section generates a load current based on the load current setting signal to drive the load. The reference voltage generating section generates a reference voltage based on the load current setting signal. The drive voltage generating section generates a drive voltage, supplies the drive voltage to the load, generates a between-both-terminals voltage between both terminals of the load current generating section based on the drive voltage and controls the drive voltage so that the difference between the between-both-terminals voltage and the reference voltage becomes small.

摘要翻译： 根据本发明的负载驱动装置包括负载电流设定信号生成部，负载电流产生部，基准电压生成部和驱动电压生成部。 负载电流设定信号生成部生成期望的负载电流设定信号。 负载电流产生部根据负载电流设定信号生成负载电流，驱动负载。 参考电压产生部分基于负载电流设置信号产生参考电压。 驱动电压产生部生成驱动电压，向驱动电压供给驱动电压，根据驱动电压在负载电流产生部的两端之间产生两端电压，并控制驱动电压， 两端电压和参考电压变小。

公开(公告)号：US20080046695A1

公开(公告)日：2008-02-21

申请号：US11790266

申请日：2007-04-24

申请人： Takaharu Ishizuka ,  Toshikazu Ueki ,  Makoto Hataida ,  Takashi Yamamoto ,  Yuka Hosokawa ,  Takeshi Owaki ,  Daisuke Itou

发明人： Takaharu Ishizuka ,  Toshikazu Ueki ,  Makoto Hataida ,  Takashi Yamamoto ,  Yuka Hosokawa ,  Takeshi Owaki ,  Daisuke Itou

IPC分类号： G06F9/30 ,  G06F12/00

CPC分类号： G06F13/1642

摘要： In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.

摘要翻译： 在包括CPU发出的请求队列的系统控制器中，具有处理具有相同地址的多个请求的电路不被输入到CPU发出的请求队列，除了高速缓存替换请求以外的最新请求被保留 部分。 因此，即使发出的请求高速缓存替换请求的地址与CPU发出的请求队列所保留的请求的地址相匹配，也不会重新发出对高速缓存替换请求的发出请求，而是在CPU发出的请求队列中排队 当发出的缓存替换请求的地址与输入请求保留部分保留的整个地址不匹配时。

公开(公告)号：US20080046663A1

公开(公告)日：2008-02-21

申请号：US11790263

申请日：2007-04-24

申请人： Takaharu Ishizuka ,  Toshikazu Ueki ,  Makoto Hataida ,  Takashi Yamamoto ,  Yuka Hosokawa ,  Takeshi Owaki ,  Daisuke Itou

发明人： Takaharu Ishizuka ,  Toshikazu Ueki ,  Makoto Hataida ,  Takashi Yamamoto ,  Yuka Hosokawa ,  Takeshi Owaki ,  Daisuke Itou

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F12/0831

摘要： In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.

摘要翻译： 在多处理器系统中，系统控制器包括窥探标签，这些标签是由各个CPU保留的缓存标签上的复制信息。 如果在连接到同一CPU总线的每个CPU的缓存标签中的S（共享状态）中登记相同的地址，则只在与CPU对应的任何一个snoop标签中的S（共享状态）中注册该地址 其中注册了相同的地址。

公开(公告)号：US08775891B2

公开(公告)日：2014-07-08

申请号：US12763551

申请日：2010-04-20

申请人： Junji Ichimiya ,  Hiroshi Nakayama ,  Daisuke Itou ,  Shintaro Itozawa

发明人： Junji Ichimiya ,  Hiroshi Nakayama ,  Daisuke Itou ,  Shintaro Itozawa

IPC分类号： H04L1/18

CPC分类号： H04L1/1854

摘要： A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period.

摘要翻译： 发送电路经由传输路径发送附加了错误检测码的数据到接收电路。 当检测到通过传输路径接收到的数据的错误时，接收电路向发送电路发送检测到错误的数据的重传请求。 接收电路使用接收到的数据的错误检测作为触发进入终端单元调整周期，并且将在传输路径的终止处安装的接收侧终端单元的电阻值更新为终止单元调整周期内的适当值。

公开(公告)号：US08181064B2

公开(公告)日：2012-05-15

申请号：US12659896

申请日：2010-03-24

申请人： Takeshi Owaki ,  Takaharu Ishizuka ,  Toshikazu Ueki ,  Makoto Hataida ,  Yuka Hosokawa ,  Atsushi Morosawa ,  Takashi Yamamoto ,  Daisuke Itou

发明人： Takeshi Owaki ,  Takaharu Ishizuka ,  Toshikazu Ueki ,  Makoto Hataida ,  Yuka Hosokawa ,  Atsushi Morosawa ,  Takashi Yamamoto ,  Daisuke Itou

IPC分类号： G06F11/00

CPC分类号： G06F11/1658 ,  G06F11/165 ,  G06F11/1679 ,  G06F2201/81

摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.

摘要翻译： 当检测到冗余CPU的同步中断时，北桥停止发生错误的异常CPU总线的操作，并且固件集线器中的固件指示北桥禁止外部指令。 此外，固件还可以将连接到普通CPU总线的普通CPU的内部信息和高速缓存数据保存在存储器上，并且北桥将重置到家庭系统板中的所有CPU。 然后，固件将保存在存储器上的CPU的内部信息恢复到所有CPU，并指示北桥取消对外部指令的禁止。