公开(公告)号：US5745709A

公开(公告)日：1998-04-28

申请号：US497864

申请日：1995-07-03

申请人： Ichiro Okabayashi ,  Katsuyuki Kaneko ,  Hiroshi Kadota

发明人： Ichiro Okabayashi ,  Katsuyuki Kaneko ,  Hiroshi Kadota

IPC分类号： G06F15/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/173 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F15/17375 ,  G06F13/4022

摘要： A data transfer apparatus for providing efficient data transfer between one memory device and multiple devices by providing high speed switching of the multiple devices according to a count of the number of the data transfers performed between the one memory device and any of the multiple devices. The data transfer apparatus comprises a transferring unit for controlling a data transfer between the memory and a device; a counting unit for counting one each time data is transferred; and a selecting unit for selecting a device in accordance with a count value by decoding the count value output from the counting unit. The transferring unit controls the data transfer between the memory and the device selected by the selecting unit. The above data transfer apparatus may include the counting unit consisting of n-bits of a binary counter, 2.sup.n devices, and the selecting unit consisting of a decoder that inputs n-bits and outputs 2.sup.n -bits of data.

摘要翻译： 一种数据传送装置，用于通过根据在一个存储装置与多个装置中的任一个之间执行的数据传送的次数的计数，提供多个装置的高速切换，从而在一个存储装置与多个装置之间提供有效的数据传送。 数据传送装置包括用于控制存储器和装置之间的数据传送的传送单元; 计数单元，每次数据传送一次; 以及选择单元，用于通过解码从计数单元输出的计数值来根据计数值来选择设备。 传送单元控制由选择单元选择的存储器和设备之间的数据传输。 上述数据传送装置可以包括由二进制计数器的n位组成的计数单元，2n个装置，以及由输入n位并输出2n位数据的解码器组成的选择单元。

公开(公告)号：US5500830A

公开(公告)日：1996-03-19

申请号：US322507

申请日：1994-10-17

申请人： Ichiro Okabayashi

发明人： Ichiro Okabayashi

IPC分类号： G06F12/00 ,  G06F9/38 ,  G06F13/28 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4243

摘要： In a memory access device, each of read and write addresses generated by read and write address generating means is stored in a read or write address buffer through a read or write address latch. The memory is accessed based on an address supplied by either address buffer from the bottom side thereof. Each address generating means is arranged such that, when a generated address is stored in the corresponding address buffer, the address calculation stage is finished. Exception detecting means is arranged to conduct exception detection on each address before the address is supplied from the corresponding address buffer, i.e., while the address is being latched by the corresponding address latch. Accordingly, the exception detection on each address can be conducted independently from a pipeline operation, thus shortening the execution time of each calculation stage. This prevents the calculation stage from forming a critical path.

摘要翻译： 在存储器存取装置中，由读写地址产生装置生成的读地址和写地址中的每一个通过读或写地址锁存器存储在读或写地址缓冲器中。 基于地址缓冲器从其底部提供的地址访问存储器。 每个地址生成装置被布置成使得当生成的地址存储在相应的地址缓冲器中时，地址计算阶段结束。 异常检测装置被布置为在从相应的地址缓冲器提供地址之前，即，当地址被相应的地址锁存器锁存时，对每个地址进行异常检测。 因此，可以独立于流水线操作对每个地址进行异常检测，从而缩短每个计算阶段的执行时间。 这防止计算阶段形成关键路径。

公开(公告)号：US5388220A

公开(公告)日：1995-02-07

申请号：US853249

申请日：1992-03-18

申请人： Ichiro Okabayashi

发明人： Ichiro Okabayashi

IPC分类号： G06F13/40 ,  G06F15/17 ,  G06F13/00

CPC分类号： G06F15/17 ,  G06F13/4022

摘要： A parallel processing system consists of a plurality of processor elements and a network for connecting the processor elements to each other. The processor elements include a processor, a memory and a data transfer apparatus, all connected to a common bus. The data transfer apparatus includes three buffers, while a data relay includes two buffers. In data transfer from a processor element to another processor element, a data is relayed in a third processor element only with use of a buffer, or a write/read operation is not performed in the third processor element. Then, the overhead is decreased and the transfer capability is improved. Further, the data transfer apparatus does not access the common bus, so that the width of the bus can be increased, and the processing performance of the processor can be improved.

摘要翻译： 并行处理系统由多个处理器元件和用于将处理器元件彼此连接的网络组成。 处理器元件包括全部连接到公共总线的处理器，存储器和数据传送装置。 数据传送装置包括三个缓冲器，而数据继电器包括两个缓冲器。 在从处理器元件到另一个处理器元件的数据传输中，数据仅在使用缓冲器的情况下在第三处理器元件中被中继，或者在第三处理器元件中不执行写入/读取操作。 然后，开销降低，转移能力提高。 此外，数据传送装置不访问公共总线，从而可以增加总线的宽度，并且可以提高处理器的处理性能。