Delay correction for on-time generator circuitry

    公开(公告)号:US12191861B2

    公开(公告)日:2025-01-07

    申请号:US18169138

    申请日:2023-02-14

    Abstract: A circuit includes a comparator having first and second comparator inputs and a comparator output. A discharge switch is coupled between the first comparator input and a ground terminal. A capacitor has first and second capacitor terminals, in which the first capacitor terminal is coupled to the first comparator input. A delay correction circuit includes a sample-hold circuit coupled to the first capacitor terminal and the second capacitor terminal. An amplifier has a first amplifier input coupled to a hold output of the sample-hold circuit and a second amplifier input coupled to the second comparator input. A variable resistor is coupled between the second capacitor terminal and the ground terminal, and has a control input coupled to the amplifier output.

    System and method for improving efficiency for quasi-square wave power converters

    公开(公告)号:US09660531B1

    公开(公告)日:2017-05-23

    申请号:US14932705

    申请日:2015-11-04

    CPC classification number: H02M3/1588 Y02B70/1466

    Abstract: A power converter includes a power stage having a switch-node of a switched-mode power supply that is coupled to an input voltage node by a power field-effect transistor (FET) to energize an inductive circuit and is coupled to a ground node by a synchronous rectifier in parallel with the inductive circuit. The power converter also includes a controller coupled to the power stage. The controller controls switching of the power FET and synchronous rectifier in a complimentary manner. The controller switches on the power FET during a first switching cycle. Subsequently, the controller switches on the synchronous rectifier and, in response to a current through the inductive circuit being approximately zero, switches off the synchronous rectifier. Subsequently, the controller switches on the synchronous rectifier again to generate a negative current through the inductive circuit prior to entering a second switching cycle.

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