公开(公告)号：US07602043B2

公开(公告)日：2009-10-13

申请号：US11461344

申请日：2006-07-31

申请人： Eun-Cheol Lee ,  Won-Suk Yang ,  Jin-Woo Lee ,  Tae-Young Chung

发明人： Eun-Cheol Lee ,  Won-Suk Yang ,  Jin-Woo Lee ,  Tae-Young Chung

IPC分类号： H01L27/06 ,  H01L27/08

CPC分类号： H01L28/91 ,  G11C11/4091

摘要： A coupling capacitor and a semiconductor memory device using the same are provided. In an embodiment, each memory cell of the semiconductor memory device includes a coupling capacitor so that a storage capacitor can store at least 2 bits of data. The coupling capacitor has a capacitance having a predetermined ratio with respect to the capacitance of the storage capacitor. For this, the coupling capacitor is formed by substantially the same fabrication process as the storage capacitor. The predetermined ratio is obtained by choosing an appropriate number of individual capacitors, each with the same capacitance of the storage capacitor, to comprise the coupling capacitor. Also, the coupling capacitor is disposed on an interlayer insulating layer that buries a bit line in a cell region and a sense amplifier in a sense amplifier region.

摘要翻译： 提供耦合电容器和使用该耦合电容器的半导体存储器件。 在一个实施例中，半导体存储器件的每个存储单元包括耦合电容器，使得存储电容器可以存储至少2位的数据。 耦合电容器具有相对于存储电容器的电容具有预定比率的电容。 为此，耦合电容器通过与存储电容器基本上相同的制造工艺来形成。 通过选择适当数量的各个具有相同电容的存储电容器的单个电容器来获得预定比率，以包括耦合电容器。 此外，耦合电容器设置在掩埋单元区域中的位线和读出放大器区域中的读出放大器的层间绝缘层上。

公开(公告)号：US06855590B2

公开(公告)日：2005-02-15

申请号：US10650089

申请日：2003-08-28

申请人： Sang-Hun Seo ,  Seung-Hyun Park ,  Han-Sin Lee ,  Moo-Sung Kim ,  Won-Suk Yang

发明人： Sang-Hun Seo ,  Seung-Hyun Park ,  Han-Sin Lee ,  Moo-Sung Kim ,  Won-Suk Yang

IPC分类号： H01L27/092 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6659

摘要： A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

摘要翻译： 降低了栅极感应漏极泄漏（GIDL）效应的CMOS半导体器件及其制造方法。 在本发明的半导体器件中，PMOS晶体管的高浓度源极/漏极区远离栅极图案侧壁间隔物形成。 这是通过使用形成在半导体衬底的整个表面上的电介质膜作为注入掩模来实现的，其中半导体衬底包括n阱中的PMOS晶体管区域，由PMOS晶体管形成的PMOS晶体管的低浓度源极/漏极区域 使用栅极图案作为注入掩模，PMOS晶体管栅极图案侧壁间隔物以及NMOS阱中的NMOS晶体管区域，NMOS晶体管具有低浓度和高浓度源极/漏极区域。

公开(公告)号：US06337267B1

公开(公告)日：2002-01-08

申请号：US09347821

申请日：1999-07-02

申请人： Won-Suk Yang

发明人： Won-Suk Yang

IPC分类号： H01L218242

CPC分类号： H01L21/7681 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/91

摘要： A method for fabricating a semiconductor device, wherein a dual damascene metal line is formed utilising a material layer pattern. The material layer pattern has openings to define contact holes both for metal interconnection in the peripheral region and for storage nodes in the cell array region. The material layer pattern is formed on an insulating layer. A second insulating layer is deposited on the material layer pattern. A groove mask pattern is formed and used as an etch stop while etching through the etching is performed at the another insulating layer and stopped at the material layer to form a first opening. Using the material layer pattern, exposed portions of the insulating layer are etched to form a second opening aligned to the first opening and thereby to form a dual damascene opening for a metal line. Metal is deposited in the first and second opening to form dual damascene metal lines.

摘要翻译： 一种用于制造半导体器件的方法，其中利用材料层图案形成双镶嵌金属线。 材料层图案具有用于限定外围区域中的金属互连和电池阵列区域中的存储节点的接触孔的开口。 材料层图案形成在绝缘层上。 第二绝缘层沉积在材料层图案上。 形成凹槽掩模图案并将其用作蚀刻停止层，同时通过蚀刻蚀刻在另一绝缘层处进行蚀刻并停留在材料层上以形成第一开口。 使用材料层图案，蚀刻绝缘层的暴露部分以形成与第一开口对准的第二开口，从而形成用于金属线的双镶嵌开口。 金属沉积在第一和第二开口中以形成双镶嵌金属线。