利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.015 秒)

    Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect
    1.
    发明授权
    Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect 有权
    制造半导体器件的方法，旨在防止由于栅极引起的漏极泄漏效应引起的漏电流的发生

    公开(公告)号：US06855590B2

    公开(公告)日：2005-02-15

    申请号：US10650089

    申请日：2003-08-28

    申请人： Sang-Hun Seo ,  Seung-Hyun Park ,  Han-Sin Lee ,  Moo-Sung Kim ,  Won-Suk Yang

    发明人： Sang-Hun Seo ,  Seung-Hyun Park ,  Han-Sin Lee ,  Moo-Sung Kim ,  Won-Suk Yang

    IPC分类号： H01L27/092 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6659

    摘要： A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

    摘要翻译： 降低了栅极感应漏极泄漏（GIDL）效应的CMOS半导体器件及其制造方法。 在本发明的半导体器件中，PMOS晶体管的高浓度源极/漏极区远离栅极图案侧壁间隔物形成。 这是通过使用形成在半导体衬底的整个表面上的电介质膜作为注入掩模来实现的，其中半导体衬底包括n阱中的PMOS晶体管区域，由PMOS晶体管形成的PMOS晶体管的低浓度源极/漏极区域 使用栅极图案作为注入掩模，PMOS晶体管栅极图案侧壁间隔物以及NMOS阱中的NMOS晶体管区域，NMOS晶体管具有低浓度和高浓度源极/漏极区域。

    Trench isolation method for semiconductor device
    2.
    发明授权
    Trench isolation method for semiconductor device 失效
    半导体器件的沟槽隔离方法

    公开(公告)号：US6121110A

    公开(公告)日：2000-09-19

    申请号：US124093

    申请日：1998-07-29

    申请人： Soo-jin Hong ,  Yu-gyun Shin ,  Han-sin Lee ,  Hyun-cheol Choe

    发明人： Soo-jin Hong ,  Yu-gyun Shin ,  Han-sin Lee ,  Hyun-cheol Choe

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76224

    摘要： A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.

    摘要翻译： 提供沟槽隔离方法。 在沟槽隔离方法中，顺序地在半导体衬底上形成衬垫氧化膜，氧化膜和蚀刻掩模膜，然后在半导体衬底的场区域中形成沟槽。 通过氧化半导体衬底，在沟槽的内壁和氧化膜的侧壁上形成氧化膜。 在用电介质材料填充沟槽之后，去除在活性区域中形成的衬垫氧化膜，氧化膜和蚀刻掩模膜。

    Multi-level semiconductor device and method of fabricating the same
    4.
    发明申请
    Multi-level semiconductor device and method of fabricating the same 有权
    多级半导体器件及其制造方法

    公开(公告)号：US20070181882A1

    公开(公告)日：2007-08-09

    申请号：US11703649

    申请日：2007-02-08

    申请人： Han-Sin Lee

    发明人： Han-Sin Lee

    IPC分类号： H01L29/10

    CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1108

    摘要： A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.

    摘要翻译： 多级半导体器件包括半导体衬底上的第一晶体管，第一晶体管包括第一源/漏区，半导体衬底上的半导体层，半导体层上的第二晶体管，第二晶体管包括第二源/ 漏极区域，以及从所述第一源极/漏极区域延伸并接触所述半导体层的第二部分的接触图案，其中所述半导体层的所述第二部分具有大于所述半导体层的第二部分的杂质浓度 的第二源极/漏极区域。

    Method of forming isolation film for semiconductor devices
    5.
    发明授权
    Method of forming isolation film for semiconductor devices 失效
    形成半导体器件隔离膜的方法

    公开(公告)号：US06258726B1

    公开(公告)日：2001-07-10

    申请号：US09412888

    申请日：1999-10-05

    申请人： Tai-Su Park ,  Yu-gyun Shin ,  Han-sin Lee ,  Kyung-won Park

    发明人： Tai-Su Park ,  Yu-gyun Shin ,  Han-sin Lee ,  Kyung-won Park

    IPC分类号： H01L21302

    CPC分类号： H01L21/76224

    摘要： A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.

    摘要翻译： 形成隔离膜的方法形成用于将有源区域的边缘连接到隔离膜的间隔物。 间隔物位于沟槽的上侧壁上，并平滑了隔离膜的电平与有源区的电平之间的转变或台阶。 因此，可以在随后的工艺中在整个有源区上形成均匀厚度的栅极氧化膜，从而防止栅极氧化膜的特性劣化。 间隔物可以使用用于形成沟槽的硬掩模上的侧壁间隔物形成。 侧壁间隔件保护形成在沟槽中的隔离部分，并且在去除侧壁间隔物之后的蚀刻可围绕被保护部分以形成隔离物。 此外，为了消除隔离膜中的应力和缺陷，隔离膜的致密化退火可以在诸如约1150℃的高温下进行，因为间隔物减轻了隔离膜的收缩或下垂的影响。

    Semiconductor device and methods of manufacturing the same
    7.
    发明申请
    Semiconductor device and methods of manufacturing the same 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20050151173A1

    公开(公告)日：2005-07-14

    申请号：US11022809

    申请日：2004-12-28

    申请人： Sang-Hun Seo ,  Seung-Hyun Park ,  Han-Sin Lee ,  Moo-Sung Kim ,  Won-Suk Yang

    发明人： Sang-Hun Seo ,  Seung-Hyun Park ,  Han-Sin Lee ,  Moo-Sung Kim ,  Won-Suk Yang

    IPC分类号： H01L27/092 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L21/2652 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

    摘要： A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

    摘要翻译： 降低了栅极感应漏极泄漏（GIDL）效应的CMOS半导体器件及其制造方法。 在本发明的半导体器件中，PMOS晶体管的高浓度源极/漏极区远离栅极图案侧壁间隔物形成。 这是通过使用形成在半导体衬底的整个表面上的电介质膜作为注入掩模来实现的，其中半导体衬底包括n阱中的PMOS晶体管区域，由PMOS晶体管形成的PMOS晶体管的低浓度源极/漏极区域 使用栅极图案作为注入掩模，PMOS晶体管栅极图案侧壁间隔物以及NMOS阱中的NMOS晶体管区域，NMOS晶体管具有低浓度和高浓度源极/漏极区域。

    Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing
    8.
    发明授权
    Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing 有权
    集成电路器件隔离方法采用高选择性化学机械抛光

    公开(公告)号：US06537914B1

    公开(公告)日：2003-03-25

    申请号：US09570225

    申请日：2000-05-12

    申请人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee ,  Jung-yup Kim ,  Chang-ki Hong ,  Ho-kyu Kang

    发明人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee ,  Jung-yup Kim ,  Chang-ki Hong ,  Ho-kyu Kang

    IPC分类号： H01L21302

    CPC分类号： C09G1/02 ,  C09K3/1463 ,  H01L21/31053 ,  H01L21/76224

    摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.

    摘要翻译： 用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。 特别地，蚀刻衬底表面以形成沟槽。 然后在衬底表面和沟槽中形成绝缘层。 绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。 包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。 结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

    Trench isolation structure, semiconductor device having the same, and trench isolation method
    9.
    发明授权
    Trench isolation structure, semiconductor device having the same, and trench isolation method 有权
    沟槽隔离结构，具有相同的半导体器件，以及沟槽隔离方法

    公开(公告)号：US06331469B1

    公开(公告)日：2001-12-18

    申请号：US09684822

    申请日：2000-10-10

    申请人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee

    发明人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee

    IPC分类号： H01L2176

    CPC分类号： H01L21/76235

    摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.

    摘要翻译： 一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应 提供沟槽隔离方法。 在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。 在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。 在内壁氧化膜的表面上形成衬垫。 沟槽填充有电介质膜。 蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

    Trench isolation regions having trench liners with recessed ends
    10.
    发明授权
    Trench isolation regions having trench liners with recessed ends 有权
    具有凹槽端的沟槽衬套的沟槽隔离区

    公开(公告)号：US06465866B2

    公开(公告)日：2002-10-15

    申请号：US09911096

    申请日：2001-07-23

    申请人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee

    发明人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee

    IPC分类号： H01L2176

    CPC分类号： H01L21/76235

    摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.

    摘要翻译： 一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应 提供沟槽隔离方法。 在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。 在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。 在内壁氧化膜的表面上形成衬垫。 沟槽填充有电介质膜。 蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。