公开(公告)号：US5766369A

公开(公告)日：1998-06-16

申请号：US726181

申请日：1996-10-04

Applicant: Toan Tran ,  Michael F. Brenner

Inventor： Toan Tran ,  Michael F. Brenner

IPC: B08B7/02 ,  B81B3/00 ,  G02B26/08 ,  H01L21/306

CPC classification number: H01L21/02043 ,  B08B7/02 ,  B81C1/00849 ,  G02B26/0833

Abstract: An improved process for manufacturing semiconductor devices (10). The device, which could be a semiconductor wafer, an individual chip, or a device that has integrated within it semiconductor devices, such as a compact disk drive, is placed or held upside down with its working surface (12) open. The device (10) is struck, causing particulates (18) attached to the working surface (12) to fall free of the device. Alternately, the device could be sharply decelerated to apply the shock. Additionally, the device could be held substantially vertical and rotated to use centrifugal force to separate the particulates away from the device.

Abstract translation: 一种用于制造半导体器件（10）的改进方法。 可以是半导体晶片，单个芯片或集成在其中的半导体器件（例如光盘驱动器）的器件，其工作表面（12）打开而被倒置或保持。 撞击装置（10），使附接到工作表面（12）的颗粒（18）脱离装置。 或者，该装置可以急剧减速以应用冲击。 另外，该装置可以被保持为基本垂直并旋转以使用离心力将颗粒分离离开装置。

公开(公告)号：US5432476A

公开(公告)日：1995-07-11

申请号：US44949

申请日：1993-04-09

Applicant: Toan Tran

Inventor： Toan Tran

IPC: H03F3/45

CPC classification number: H03F3/45076

Abstract: A differential to single-ended converter includes a voltage-to-current converter that converts differential voltage input signals to differential current signals which differ by a difference current. A current mirror mirrors the first differential current signal. A substantially constant DC voltage level is established. A resistor conducts any difference in current between the mirrored current and the second differential current signal and translates this difference current to a single-ended voltage output signal. An input buffer provides the differential voltage input signals to the voltage-to-current converters.

Abstract translation: 差分到单端转换器包括电压 - 电流转换器，其将差分电压输入信号转换为差分电流差分电流信号。 电流镜反射第一个差分电流信号。 建立基本恒定的直流电压电平。 电阻器在镜像电流和第二差分电流信号之间导通电流的任何差异，并将该差分电流转换为单端电压输出信号。 输入缓冲器向电压 - 电流转换器提供差分电压输入信号。

公开(公告)号：US07560792B2

公开(公告)日：2009-07-14

申请号：US11626624

申请日：2007-01-24

Applicant: Rajesh Khamankar ,  Douglas T. Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James J. Chambers

Inventor： Rajesh Khamankar ,  Douglas T. Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James J. Chambers

IPC: H01L27/105

CPC classification number: H01L21/823462 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).

Abstract translation: 在用于MOS晶体管制造的半导体衬底上形成双栅介质层。 第一电介质层（30）形成在半导体衬底（10）上。 在所述第一介电层上进行第一等离子体氮化处理。 在衬底的区域中去除第一电介质层（30），并且在这些区域中形成第二电介质层（50）。 在第一电介质层和第二电介质层上进行第二等离子体氮化处理。 然后使用电介质层（30,50）制造MOS晶体管（160,170）。

公开(公告)号：US07183165B2

公开(公告)日：2007-02-27

申请号：US10702234

申请日：2003-11-06

Applicant: Rajesh Khamankar ,  Douglas T. Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James J. Chambers

Inventor： Rajesh Khamankar ,  Douglas T. Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James J. Chambers

IPC: H01L21/336

CPC classification number: H01L21/823462 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).

Abstract translation: 在用于MOS晶体管制造的半导体衬底上形成双栅介质层。 第一电介质层（30）形成在半导体衬底（10）上。 在所述第一介电层上进行第一等离子体氮化处理。 在衬底的区域中去除第一电介质层（30），并且在这些区域中形成第二电介质层（50）。 在第一电介质层和第二电介质层上进行第二等离子体氮化处理。 然后使用电介质层（30,50）制造MOS晶体管（160,170）。

公开(公告)号：US20050269334A1

公开(公告)日：2005-12-08

申请号：US10990125

申请日：2004-11-16

Applicant: Won Bang ,  Toan Tran ,  Yen-Kun Wang

Inventor： Won Bang ,  Toan Tran ,  Yen-Kun Wang

IPC: E05F11/38 ,  H01L21/00

CPC classification number: H01L21/67126

Abstract: Techniques for a door system for sealing an opening between two chambers in a semiconductor processing system are described. A sealing member seals the opening when a door is in a closed position. To selectively open and close the opening, an actuator moves the door. A valve actuator switch provides a first or second pressure to the actuator depending on the pressure inside a first chamber. In one embodiment, a sensor monitors the pressure inside the first chamber.

Abstract translation: 描述了用于密封半导体处理系统中的两个室之间的开口的门系统的技术。 当门处于关闭位置时，密封构件密封开口。 为了选择性地打开和关闭开口，致动器移动门。 阀致动器开关根据第一室内的压力向致动器提供第一或第二压力。 在一个实施例中，传感器监测第一室内的压力。

公开(公告)号：US20050152752A1

公开(公告)日：2005-07-14

申请号：US10755178

申请日：2004-01-12

Applicant: Toan Tran

Inventor： Toan Tran

IPC: B23C5/00 ,  B23C5/06 ,  B23C5/20 ,  B23C5/22 ,  B23C5/28

CPC classification number: B23C5/06 ,  B23C5/006 ,  B23C5/2208 ,  B23C5/28 ,  B23C2200/0461 ,  B23C2210/02 ,  B23C2210/243 ,  B23C2270/16 ,  Y10T407/1908 ,  Y10T407/1946 ,  Y10T407/2206

Abstract: A milling cutter with two faces of cutting end and two mirror symmetrical central bores for the mounting in a shell mill holder on either one of them. The aligned key grooves are formed on the bottom surface of each central bore. The inserts are located on the periphery of each cutting end.

Abstract translation: 铣刀具有两个切割端面和两个反光镜对称的中心孔，用于安装在其中任何一个的外壳磨机架上。 对准的键槽形成在每个中心孔的底表面上。 插入件位于每个切割端的周边。

公开(公告)号：US4792835A

公开(公告)日：1988-12-20

申请号：US938226

申请日：1986-12-05

Applicant: Stephen P. Sacarisen ,  Gene E. Blankenship ,  Rajiv R. Shah ,  Toan Tran ,  David J. Myers ,  Johnson J. Lin ,  Steve Thompson

Inventor： Stephen P. Sacarisen ,  Gene E. Blankenship ,  Rajiv R. Shah ,  Toan Tran ,  David J. Myers ,  Johnson J. Lin ,  Steve Thompson

IPC: H01L21/82 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  H01L27/112 ,  H01L29/78 ,  B44C1/22 ,  C23F1/02 ,  H01L21/00

CPC classification number: H01L23/5256 ,  H01L2924/0002

Abstract: A process for making a metal fuse link in a MOS or CMOS process which includes depositing a refractory metal or metal alloy over an already deposited multi-level oxide and patterning the deposited metal or metal alloy so that it has a fusing segment between and integral with expanded segments such that the length and cross sectional area of the fusing segment is sufficiently small so that the fusing current therethrough is less than 20 milliamperes. The fuse and surrounding circuitry is covered with a passivation layer and contacts formed in the passivation layer to the expanded segments.

Abstract translation: 一种用于在MOS或CMOS工艺中制造金属熔断体的工艺，其包括在已沉积的多层氧化物上沉积难熔金属或金属合金，并对沉积的金属或金属合金进行图案化，使得其具有与 扩展段使得熔断段的长度和横截面面积足够小，使得其中的熔化电流小于20毫安。 保险丝和周围电路覆盖有钝化层和形成在钝化层中的扩展段的触点。