公开(公告)号：US20110316595A1

公开(公告)日：2011-12-29

申请号：US12824982

申请日：2010-06-28

申请人： Eric K. Bolton

发明人： Eric K. Bolton

IPC分类号： H03L7/085

CPC分类号： H03L7/099 ,  H03L1/022 ,  H03L2207/06

摘要： The present invention discloses a continuous voltage controlled oscillator (VCO) frequency temperature compensation apparatus for a phase locked loop (PLL) and a continuous VCO frequency temperature compensation method for a PLL. The system utilizes a VCO with one digital coarse tuning input, a first analog fine tuning input, and a second analog fine tuning input. The system uses the second analog fine tuning inputs to compensate the VCO for frequency shifts due to temperature fluctuation. When the PLL transitions to the fine lock (FL) mode, the system starts driving the second fine tuning input with a differential amplifier. The differential amplifier compares the first fine tuning input with a reference voltage, and drives the second fine tuning input to compensate the first fine tuning input.

摘要翻译： 本发明公开了一种用于锁相环（PLL）的连续压控振荡器（VCO）频率温度补偿装置和用于PLL的连续VCO频率温度补偿方法。 该系统利用具有一个数字粗调输入，第一模拟微调输入和第二模拟微调输入的VCO。 该系统使用第二个模拟微调输入来补偿VCO由于温度波动引起的频移。 当PLL转换到精细锁定（FL）模式时，系统利用差分放大器开始驱动第二个微调输入。 差分放大器将第一个微调输入与参考电压进行比较，并驱动第二个微调输入以补偿第一个微调输入。

公开(公告)号：US20110304365A1

公开(公告)日：2011-12-15

申请号：US12816059

申请日：2010-06-15

申请人： Ryan Lee Bunch

发明人： Ryan Lee Bunch

IPC分类号： H03L7/08

CPC分类号： H03L7/1976 ,  H03L2207/06

摘要： The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode. This loop works by comparing the output voltage of the FLL DAC to the LPF output voltage, and then using this value to modulate the divider's dividing value. After the secondary feedback loop settles, output voltage from the LPF will be equal to the value that can drive the VCO to the desired lock frequency, and the phase error at the input side of the PFD produces a zero-average current to the charge pump. When this condition is set, the loop is essentially already in phase lock and the lock transient from the FLL mode to the PLL mode will be minimal.

摘要翻译： 本发明提供了围绕现有FLL的第二反馈回路，其迫使N分压器（NDIV），PFD，CP和LPF的路径上的信号基本上在FLL关闭之前达到其期望的锁定状态，并且系统 进入PLL模式。 该循环通过将FLL DAC的输出电压与LPF输出电压进行比较，然后使用该值来调制除法器的除法值。 在次级反馈环路稳定后，来自LPF的输出电压将等于可将VCO驱动到所需锁定频率的值，PFD输入侧的相位误差会产生零电平至电荷泵 。 当设置此条件时，环路本质上已经处于相位锁定状态，并且从FLL模式到PLL模式的锁定瞬变将很小。

公开(公告)号：US08045597B2

公开(公告)日：2011-10-25

申请号：US10548448

申请日：2004-03-08

申请人： Francesc Bolxadera Espax

发明人： Francesc Bolxadera Espax

IPC分类号： H04B1/00

CPC分类号： H04B1/70775 ,  H04B1/709 ,  H04B1/7113

摘要： A method of multi-path searching in a cellular network is provided. The method carries out a correlation process over a predetermined integration period in relation to a first pilot signal received in connection with a first cell of the cellular network to generate first multiple correlation measurements corresponding to a plurality of time delays in the signal, analyzing the first multiple correlation measurements in relation to the time delays to identify multi-path positions in the signal. Information of the multi-path positions over a first predetermined integration period is stored as a first set of candidate multi-path positions and compared with a second set of candidate multi-path positions derived from second multiple correlation measurements corresponding to the time delays over a second predetermined integration period in relation to the first pilot signal, so as to confirm or reject candidate multi-path positions and define modified candidate multi-path positions.

摘要翻译： 提供了一种在蜂窝网络中进行多路径搜索的方法。 该方法相对于与蜂窝网络的第一小区相关联地接收的第一导频信号在预定的积分周期上执行相关处理，以产生对应于信号中的多个时间延迟的第一多个相关测量，分析第一个 相关于时间延迟的多个相关测量来识别信号中的多径位置。 将第一预定积分期间的多路径位置的信息存储为候选多路径位置的第一组，并与第二组候选多路径位置进行比较，该第二组候选多路径位置从对应于时间延迟的第二多个相关测量 相对于第一导频信号的第二预定积分周期，以便确认或拒绝候选多径位置并定义修改的候选多径位置。

公开(公告)号：US08044851B2

公开(公告)日：2011-10-25

申请号：US12759902

申请日：2010-04-14

申请人： Mikhail Kholostov ,  Alexander Fedotov ,  Nikolay Mikhaylov ,  Bijan Jalali

发明人： Mikhail Kholostov ,  Alexander Fedotov ,  Nikolay Mikhaylov ,  Bijan Jalali

IPC分类号： G01S19/22

CPC分类号： G01S19/22 ,  G01S19/52

摘要： A method of multipath error suppression in a satellite navigation receiver, including steps of navigation satellites signals searching, receiving and processing complex signals from each satellite, tracking found signals with a following-up open loop and determining coordinates, receiver velocity and exact time based on measurements of direct and reflected signal delay and Doppler frequency, the method including: forming, on the basis of navigation parameters, a two-dimensional accumulated power grid, calculating single-path signal corrections using the centered accumulated power grid determining, whether a multipath is presented, and performing, in case of positive result of this determination, improvement of corrections using weights, wherein, performing improvement of corrections using weights is carried out by forming a likelihood function on the basis of a centered accumulated powers vector, and correction is performed according to the found likelihood function global maximum.

摘要翻译： 一种卫星导航接收机的多路径误差抑制方法，包括导航卫星信号搜索，接收和处理来自每个卫星的复信号的步骤，跟踪后续开环的发现信号，并基于以下步骤确定坐标，接收机速度和精确时间 直接和反射信号延迟和多普勒频率的测量，其方法包括：基于导航参数形成二维累积电网，使用中心累积电网计算单路信号校正，确定多径是否为 呈现和执行，在该确定的肯定结果的情况下，使用权重改进校正，其中，通过基于中心的累积功率矢量形成似然函数来执行使用权重的校正的改进，并且执行校正 根据发现的似然函数全局最大值。

公开(公告)号：US07974262B2

公开(公告)日：2011-07-05

申请号：US11659600

申请日：2005-08-05

申请人： Navid Fatemi-Ghomi ,  Cyril Valadon

发明人： Navid Fatemi-Ghomi ,  Cyril Valadon

IPC分类号： H04J3/06

CPC分类号： H04L7/0054 ,  H04B7/2681

摘要： A telecommunications network participant, comprising means for digitising, as a series of samples, a received signal containing a succession of symbols, means for measuring time misalignment between the symbols and the samples and means for applying a fractional delay to the positions of the samples to reduce the misalignment.

摘要翻译： 一种电信网络参与者，包括用于数字化作为一系列样本的包含一系列符号的接收信号的装置，用于测量符号和样本之间的时间不对准的装置，以及用于将样本的位置应用分数延迟的装置 减少不对准。

公开(公告)号：US20100265133A1

公开(公告)日：2010-10-21

申请号：US12759902

申请日：2010-04-14

申请人： Mikhail Kholostov ,  Alexander Fedotov ,  Nikolay Mikhaylov ,  Bijan Jalali

发明人： Mikhail Kholostov ,  Alexander Fedotov ,  Nikolay Mikhaylov ,  Bijan Jalali

IPC分类号： G01S19/22

CPC分类号： G01S19/22 ,  G01S19/52

摘要： A method of multipath error suppression in a satellite navigation receiver, including steps of navigation satellites signals searching, receiving and processing complex signals from each satellite, tracking found signals with a following-up open loop and determining coordinates, receiver velocity and exact time based on measurements of direct and reflected signal delay and Doppler frequency, the method including: forming, on the basis of navigation parameters, a two-dimensional accumulated power grid, calculating single-path signal corrections using the centered accumulated power grid determining, whether a multipath is presented, and performing, in case of positive result of this determination, improvement of corrections using weights, wherein, performing improvement of corrections using weights is carried out by forming a likelihood function on the basis of a centered accumulated powers vector, and correction is performed according to the found likelihood function global maximum.

摘要翻译： 一种卫星导航接收机的多路径误差抑制方法，包括导航卫星信号搜索，接收和处理来自每个卫星的复信号的步骤，跟踪后续开环的发现信号，并基于以下步骤确定坐标，接收机速度和精确时间 直接和反射信号延迟和多普勒频率的测量，其方法包括：基于导航参数形成二维累积电网，使用中心累积电网计算单路信号校正，确定多径是否为 呈现和执行，在该确定的肯定结果的情况下，使用权重改进校正，其中，通过基于中心的累积功率矢量形成似然函数来执行使用权重的校正的改进，并且执行校正 根据发现的似然函数全局最大值。

公开(公告)号：US07716442B2

公开(公告)日：2010-05-11

申请号：US10489800

申请日：2002-09-17

申请人： Eugene Pascal Herczog

发明人： Eugene Pascal Herczog

IPC分类号： G06F13/14

CPC分类号： G06F13/1605 ,  G06F13/30

摘要： Multiple data devices (A,B,C) are interfaced via a bus arbiter (S) with an external memory (F) so as to support burst-mode access by each device (A,B,C) one or more read registers (R1,R2,R3) are provided in the memory (F), and each register (R1,R2,R3) supports burst-mode access by a corresponding device (A,B,C). The arbiter (s) selects the register to be used following the initial access burst, according to the device requiring access. Thus, the memory (F) supports multiple burst-mode accesses in parallel.

摘要翻译： 多个数据设备（A，B，C）经由总线仲裁器（S）与外部存储器（F）接口，以便支持每个设备（A，B，C）的突发模式访问一个或多个读取寄存器 R1，R2，R3）设置在存储器（F）中，每个寄存器（R1，R2，R3）支持相应设备（A，B，C）的突发模式访问。 仲裁器根据需要访问的设备选择在初始接入突发之后使用的寄存器。 因此，存储器（F）并行地支持多个突发模式访问。

公开(公告)号：US07519104B2

公开(公告)日：2009-04-14

申请号：US10547426

申请日：2004-02-27

申请人： Daniel Edward Alt

发明人： Daniel Edward Alt

IPC分类号： H04B1/00

CPC分类号： H04J13/0003 ,  H04B1/707 ,  H04B2201/70707

摘要： A method for applying one or more code values to an input signal value to produce an output signal value in a CDMA communications scheme, wherein the code value or values may lie only either on or equally distant from an orthogonal pair of axes defining a two dimensional signal space, the input and output signal values each have components along each axis and the method comprises processing, via a logic function, the code value or values to produce two multiplier values and a selector value, creating two product values by multiplying the multiplier values with respective components of the input signal value, negating one of the product values to produce a third product value and selecting, on the basis of the selector signal, two of the three product values to become the components of the output signal value.

摘要翻译： 一种用于将一个或多个代码值应用于输入信号值以在CDMA通信方案中产生输出信号值的方法，其中所述代码值或值可以仅在定义二维的正交对轴对上或相等的距离上 信号空间，输入和输出信号值各自具有沿着每个轴的分量，并且该方法包括经由逻辑功能处理代码值或值以产生两个乘数值和选择器值，通过乘以乘数值来产生两个乘积值 利用输入信号值的各个分量，否定产品值之一以产生第三乘积值，并且基于选择器信号选择三个乘积值中的两个以成为输出信号值的分量。

公开(公告)号：US09448967B2

公开(公告)日：2016-09-20

申请号：US13687102

申请日：2012-11-28

申请人： MStar Semiconductor, Inc. ,  MStar Semiconductor, Inc. ,  MStar Software R&D (Shenzhen) Ltd.

发明人： Wolfgang Kuechler

IPC分类号： G06F13/00 ,  G06F15/80

CPC分类号： G06F15/8015

摘要： Techniques are provided aimed at improving the flexibility and reducing the area and power consumption of digital baseband integrated circuits by using stream data processor based modem architecture. Semiconductor companies offering baseband ICs for handsets, face the challenges of improving die size efficiency, power efficiency, performance, time to market, and coping with evolving standards. Software defined radio based implementations offer a fast time to market. Dedicated hardware designs give the best die size and power efficiency. To combine the advantages of dedicated hardware with the advantages of conventional software defined radio solutions the stream data processor is partitioned into a stream processor unit, which implements processing functions in dedicated hardware and is hence die size and power efficient, and a flexible stream control unit which may be software defined to minimize the time to market of the product.

摘要翻译： 提供了旨在通过使用基于流数据处理器的调制解调器架构来提高数字基带集成电路的灵活性和减小面积和功耗的技术。 为手机提供基带IC的半导体公司面临着提高芯片尺寸效率，电源效率，性能，上市时间以及应对不断变化的标准的挑战。 基于软件定义的基于无线电的实施提供了快速的上市时间 专用硬件设计提供最佳的裸片尺寸和功率效率。 为了将专用硬件的优点与常规软件定义的无线电解决方案的优点相结合，流数据处理器被划分为流处理器单元，其实现专用硬件中的处理功能，因此具有芯片尺寸和功率效率，以及灵活的流控制单元 这可能是软件定义的，以最小化产品的上市时间。

公开(公告)号：US20140123148A1

公开(公告)日：2014-05-01

申请号：US13687102

申请日：2012-11-28

申请人： MSTAR SEMICONDUCTOR, INC. ,  MSTAR SEMICONDUCTOR, INC. ,  MSTAR SOFTWARE R&D (SHENZHEN) LTD.

发明人： Wolfgang Kuechler

IPC分类号： G06F9/46

CPC分类号： G06F15/8015

摘要： Techniques are provided aimed at improving the flexibility and reducing the area and power consumption of digital baseband integrated circuits by using stream data processor based modem architecture. Semiconductor companies offering baseband ICs for handsets, face the challenges of improving die size efficiency, power efficiency, performance, time to market, and coping with evolving standards. Software defined radio based implementations offer a fast time to market. Dedicated hardware designs give the best die size and power efficiency. To combine the advantages of dedicated hardware with the advantages of conventional software defined radio solutions the stream data processor is partitioned into a stream processor unit, which implements processing functions in dedicated hardware and is hence die size and power efficient, and a flexible stream control unit which may be software defined to minimise the time to market of the product.

摘要翻译： 提供了旨在通过使用基于流数据处理器的调制解调器架构来提高数字基带集成电路的灵活性和减小面积和功耗的技术。 为手机提供基带IC的半导体公司面临着提高芯片尺寸效率，电源效率，性能，上市时间以及应对不断变化的标准的挑战。 基于软件定义的基于无线电的实施提供了快速的上市时间。 专用硬件设计可提供最佳的裸片尺寸和功率效率。 为了将专用硬件的优点与常规软件定义的无线电解决方案的优点相结合，流数据处理器被划分为流处理器单元，其实现专用硬件中的处理功能，因此具有芯片尺寸和功率效率，以及灵活的流控制单元 这可能是软件定义的，以最小化产品的上市时间。