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    Pre-distortion system for a synthesizer having modulation applied in the reference path
    1.
    发明授权
    Pre-distortion system for a synthesizer having modulation applied in the reference path 有权
    具有在参考路径中应用的调制的合成器的预失真系统

    公开(公告)号：US07288999B1

    公开(公告)日：2007-10-30

    申请号：US11347956

    申请日：2006-02-06

    申请人： Alexander Wayne Hietala ,  Ryan Lee Bunch ,  Scott Robert Humphreys ,  Barry Travis Hunt, Jr.

    发明人： Alexander Wayne Hietala ,  Ryan Lee Bunch ,  Scott Robert Humphreys ,  Barry Travis Hunt, Jr.

    IPC分类号： H03L7/197 ,  H04L25/49

    CPC分类号： H03L7/1976 ,  H03C3/0966 ,  H03L7/23 ,  H03L2207/12

    摘要： A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.

    摘要翻译： 提供了提供相位或频率调制信号的系统。 通常，该系统包括在PLL的参考路径中具有分数N分频器的锁相环（PLL），其操作以基于预失真调制信号来划分参考频率。 预失真电路通过对调制信号进行预失真来提供预失真调制信号，使得预失真和PLL的传递函数的卷积或级联导致范围内的基本平坦的频率响应 的调制率大于PLL的带宽。

    FAST PHASE LOCKING SYSTEM FOR AUTOMATICALLY CALIBRATED FRACTIONAL-N PLL
    2.
    发明申请
    FAST PHASE LOCKING SYSTEM FOR AUTOMATICALLY CALIBRATED FRACTIONAL-N PLL 有权
    用于自动校准分段N PLL的快速锁相系统

    公开(公告)号：US20110304365A1

    公开(公告)日：2011-12-15

    申请号：US12816059

    申请日：2010-06-15

    申请人： Ryan Lee Bunch

    发明人： Ryan Lee Bunch

    IPC分类号： H03L7/08

    CPC分类号： H03L7/1976 ,  H03L2207/06

    摘要： The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode. This loop works by comparing the output voltage of the FLL DAC to the LPF output voltage, and then using this value to modulate the divider's dividing value. After the secondary feedback loop settles, output voltage from the LPF will be equal to the value that can drive the VCO to the desired lock frequency, and the phase error at the input side of the PFD produces a zero-average current to the charge pump. When this condition is set, the loop is essentially already in phase lock and the lock transient from the FLL mode to the PLL mode will be minimal.

    摘要翻译： 本发明提供了围绕现有FLL的第二反馈回路，其迫使N分压器（NDIV），PFD，CP和LPF的路径上的信号基本上在FLL关闭之前达到其期望的锁定状态，并且系统 进入PLL模式。 该循环通过将FLL DAC的输出电压与LPF输出电压进行比较，然后使用该值来调制除法器的除法值。 在次级反馈环路稳定后，来自LPF的输出电压将等于可将VCO驱动到所需锁定频率的值，PFD输入侧的相位误差会产生零电平至电荷泵 。 当设置此条件时，环路本质上已经处于相位锁定状态，并且从FLL模式到PLL模式的锁定瞬变将很小。

    Fractional-N based digital AFC system with a translational PLL transmitter
    4.
    发明授权
    Fractional-N based digital AFC system with a translational PLL transmitter 有权
    基于分数N的数字AFC系统具有平移PLL发射机

    公开(公告)号：US07626462B1

    公开(公告)日：2009-12-01

    申请号：US11415578

    申请日：2006-05-02

    申请人： Alexander Wayne Hietala ,  Ryan Lee Bunch ,  Scott Robert Humphreys ,  Barry Travis Hunt, Jr. ,  Stephen T. Janesch

    发明人： Alexander Wayne Hietala ,  Ryan Lee Bunch ,  Scott Robert Humphreys ,  Barry Travis Hunt, Jr. ,  Stephen T. Janesch

    IPC分类号： H03L7/00

    CPC分类号： H03L7/23 ,  H03J1/005 ,  H03J7/065 ,  H03L7/1974

    摘要： A fractional-N based Automatic Frequency Control (AFC) system for a mobile terminal is provided. In general, automatic frequency control is implemented in a frequency synthesizer to correct or compensate for a frequency error of an associated reference oscillator. The frequency synthesizer includes a first fractional-N phase-locked loop (FN-PLL) generating a baseband clock signal used by a baseband processor of the mobile terminal, a second FN-PLL generating a receiver local oscillator signal used by a receiver of the mobile terminal to downconvert a received radio frequency signal to a desired frequency, and a translational PLL generating a transmitter local oscillator signal used by a transmitter of the mobile terminal to provide a radio frequency transmit signal. The automatic frequency control is performed by applying a digital correction value, which is preferably multiplicative, to fractional-N dividers of the first and second FN-PLLs.

    摘要翻译： 提供了一种用于移动终端的基于分数N的自动频率控制（AFC）系统。 通常，在频率合成器中实现自动频率控制以校正或补偿相关参考振荡器的频率误差。 频率合成器包括产生由移动终端的基带处理器使用的基带时钟信号的第一小数N锁相环（FN-PLL），第二FN-PLL产生由接收机使用的接收机本地振荡器信号 移动终端将所接收的射频信号下变频到期望的频率，以及平移PLL，其生成由移动终端的发射机使用以提供射频发射信号的发射机本地振荡器信号。 通过将优选乘法的数字校正值应用于第一和第二FN-PLL的分数N分频器来执行自动频率控制。

    Fractional-N offset phase locked loop
    5.
    发明授权
    Fractional-N offset phase locked loop 有权
    小数N偏移锁相环

    公开(公告)号：US07098754B2

    公开(公告)日：2006-08-29

    申请号：US11047258

    申请日：2005-01-31

    申请人： Scott Robert Humphreys ,  Ryan Lee Bunch ,  Barry Travis Hunt, Jr. ,  Alexander Wayne Hietala

    发明人： Scott Robert Humphreys ,  Ryan Lee Bunch ,  Barry Travis Hunt, Jr. ,  Alexander Wayne Hietala

    IPC分类号： H03C3/00 ,  H04L27/20

    CPC分类号： H03L7/1976 ,  H03C3/0966 ,  H03L7/23 ,  H03L2207/12

    摘要： A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.

    摘要翻译： 提供了一个分数N偏移锁相环（FN-OPLL）。 FN-OPLL包括分数分频器，相位检测器，环路滤波器，压控振荡器（VCO）和反馈电路。 组合器电路组合初始分数除法值和调制信号以提供组合分数除数值。 基于组合分数除法，分数N分频器划分参考频率，并向相位检测器提供分频参考频率。 相位检测器将分频参考频率的相位与反馈信号的相位进行比较，以提供比较信号。 比较信号由环路滤波器滤波，以向VCO提供控制信号，其中控制信号控制VCO的输出信号的频率。 输出信号由反馈电路处理，以将反馈信号提供给相位检测器。

    Fast phase locking system for automatically calibrated fractional-N PLL
    6.
    发明授权
    Fast phase locking system for automatically calibrated fractional-N PLL 有权
    用于自动校准分数N PLL的快速锁相系统

    公开(公告)号：US08179174B2

    公开(公告)日：2012-05-15

    申请号：US12816059

    申请日：2010-06-15

    申请人： Ryan Lee Bunch

    发明人： Ryan Lee Bunch

    IPC分类号： H03L7/06

    CPC分类号： H03L7/1976 ,  H03L2207/06

    摘要： The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode. This loop works by comparing the output voltage of the FLL DAC to the LPF output voltage, and then using this value to modulate the divider's dividing value. After the secondary feedback loop settles, output voltage from the LPF will be equal to the value that can drive the VCO to the desired lock frequency, and the phase error at the input side of the PFD produces a zero-average current to the charge pump. When this condition is set, the loop is essentially already in phase lock and the lock transient from the FLL mode to the PLL mode will be minimal.

    摘要翻译： 本发明提供围绕现有FLL的第二反馈回路，其在N分压器（NDIV），PFD，CP和LPF的路径上强制信号在FLL被关闭之前基本达到其期望的锁定状态，并且系统 进入PLL模式。 该循环通过将FLL DAC的输出电压与LPF输出电压进行比较，然后使用该值来调制除法器的除法值。 在次级反馈环路稳定后，来自LPF的输出电压将等于可将VCO驱动到所需锁定频率的值，PFD输入侧的相位误差会产生零电平至电荷泵 。 当设置此条件时，环路本质上已经处于相位锁定状态，并且从FLL模式到PLL模式的锁定瞬变将很小。