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公开(公告)号：US07386074B1
公开(公告)日：2008-06-10
申请号：US10680620
申请日：2003-10-06
Applicant: Narasimhan Venkatesh , Satya Rao , Dharani Naga Sailaja Sankabathula , Partha Sarathy Murali
Inventor： Narasimhan Venkatesh , Satya Rao , Dharani Naga Sailaja Sankabathula , Partha Sarathy Murali
IPC: H04L27/08
CPC classification number: H03G3/3068 , H03G3/3078
Abstract: An RF receiver which produces quadrature digitized outputs and has a gain control is coupled to a digital gain controller which converts the quadrature digitized outputs into an rms voltage, and iterates over a finite number of steps to quickly control the gain to a level sufficient to achieve subsequent digital signal processing without limitations caused by insufficient dynamic range or nonlinear saturation effects caused by insufficient signal or excessive signal at the A/D input, respectively.
Abstract translation: 产生正交数字化输出并具有增益控制的RF接收器耦合到数字增益控制器，该数字增益控制器将正交数字化输出转换成有效值电压，并且迭代有限数量的步骤以将增益快速控制到足以实现的水平 分别由于信号不足或A / D输入过大信号引起的动态范围不足或非线性饱和效应引起的后续数字信号处理。
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公开(公告)号：US07296100B1
公开(公告)日：2007-11-13
申请号：US10680660
申请日：2003-10-06
Applicant: Narasimhan Venkatesh , Satya Rao
Inventor： Narasimhan Venkatesh , Satya Rao
CPC classification number: G06F13/128
Abstract: A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to “used” or “free”, and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data. Data is removed from packet memory based on which queue the data may be found in. The queues are based on a priority system, where one queue receives priority over another queue for data reception and transmission.
Abstract translation: 用于无线通信系统的存储器控制器包括分组缓冲器写入系统和分组缓冲器读取系统。 分组缓冲器写入系统将包括分组报头和分组数据的分组放入分组缓冲器中。 分组缓冲器读取系统从分组缓冲器中去除包括分组报头和分组数据的分组。 分组缓冲器被布置成多个分组缓冲存储器时隙，每个时隙包括描述符状态阵列位置，包括设置为“已使用”或“空闲”的可用性位，以及包含描述符存储器时隙和数据的分组缓冲存储器位置 段内存插槽。 描述符存储器插槽包括每个分组的标题信息，并且数据段存储器时隙包括分组数据。 存储器控制器在一个或多个数据队列上操作，并且数据被放置在由从输入分组报头或分组数据导出的优先级信息确定的分组存储器中的特定队列中。 基于哪个队列可以找到数据，从数据包存储器中删除数据。队列基于优先级系统，其中一个队列通过另一个队列接收优先级以进行数据接收和传输。
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23.发明授权公开(公告)号：US11593573B2
公开(公告)日：2023-02-28
申请号：US17334890
申请日：2021-05-31
Applicant: Redpine Signals, Inc.
Inventor： Martin Kraemer , Ryan Boesch , Wei Xiong
Abstract: A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.
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24.发明申请公开(公告)号：US20220405053A1
公开(公告)日：2022-12-22
申请号：US17352373
申请日：2021-06-21
Applicant: Redpine Signals, Inc.
Inventor： Dylan FINCH
Abstract: A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which output a signed integer form fraction with a first bitwidth and a second bitwith, along with a maximum exponent. The first bitwidth signed integer form fractions are summed by an adder tree using the first bitwidth to form a first sum, and when an excess leading 0 condition is detected, a second adder tree operative on the second bitwidth integer form fractions forms a second sum. The first sum or second sum, along with the maximum exponent, is converted into floating point result.
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公开(公告)号：US20220385566A1
公开(公告)日：2022-12-01
申请号：US17334704
申请日：2021-05-29
Applicant: Redpine Signals, Inc.
Inventor： Robert WISER , Venkat MATTELA , Wei XIONG
IPC: H04L12/751
Abstract: A node mesh contains an originating node coupled to one or more nodes, each node having an communications interface input and a communications interface output. Each node has a route table with an association between a header amplitude and an output interface, such that a header having a particular amplitude causes the input node which received the message to couple the message to an associated communications interface output of the node. When the originating node outputs a message with a header amplitude, each node of the node mesh in turn directs the message to an output interface as directed by the node local route table to a terminating node of the node mesh, where the terminating node may be a training processor or inference processor for machine learning applications.
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Patent Agency Ranking
公开(公告)号：US20220385565A1
公开(公告)日：2022-12-01
申请号：US17334703
申请日：2021-05-29
Applicant: Redpine Signals, Inc.
Inventor： Robert WISER , Venkat MATTELA , Wei XIONG
IPC: H04L12/751
Abstract: A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.
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27.发明申请公开(公告)号：US20220385301A1
公开(公告)日：2022-12-01
申请号：US17334782
申请日：2021-05-30
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
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28.发明申请公开(公告)号：US20220382516A1
公开(公告)日：2022-12-01
申请号：US17334887
申请日：2021-05-31
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
Abstract: An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
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公开(公告)号：US20220382515A1
公开(公告)日：2022-12-01
申请号：US17334816
申请日：2021-05-31
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
IPC: G06F7/544
Abstract: A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.
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公开(公告)号：US11476866B2
公开(公告)日：2022-10-18
申请号：US17164689
申请日：2021-02-01
Applicant: Redpine Signals, Inc.
Inventor： Martin Kraemer , Ryan Boesch , Wei Xiong
Abstract: An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.
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