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公开(公告)号：US20220207247A1
公开(公告)日：2022-06-30
申请号：US17139226
申请日：2020-12-31
Applicant: Redpine Signals, Inc.
Inventor： Ryan BOESCH , Martin KRAEMER , Wei XIONG
Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.
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公开(公告)号：US20220385293A1
公开(公告)日：2022-12-01
申请号：US17334817
申请日：2021-05-31
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
Abstract: A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.
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公开(公告)号：US20220247422A1
公开(公告)日：2022-08-04
申请号：US17164689
申请日：2021-02-01
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
Abstract: An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.
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公开(公告)号：US20220206754A1
公开(公告)日：2022-06-30
申请号：US17139935
申请日：2020-12-31
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
Abstract: A plurality of unit elements share a charge transfer bus, each unit element accepts A and B digital inputs and generates a product P as an analog charge transferred to the charge transfer bus, each unit element comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates of each unit element are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges contributed by all unit elements to the charge transfer lines according to a bit weight and converted to a digital value output.
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公开(公告)号：US20220383002A1
公开(公告)日：2022-12-01
申请号：US17334899
申请日：2021-05-31
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
IPC: G06J1/00
Abstract: A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20220383001A1
公开(公告)日：2022-12-01
申请号：US17334890
申请日：2021-05-31
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
IPC: G06J1/00
Abstract: A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.
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7.发明申请公开(公告)号：US20220244914A1
公开(公告)日：2022-08-04
申请号：US17163494
申请日：2021-01-31
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
Abstract: A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.
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公开(公告)号：US20230146445A1
公开(公告)日：2023-05-11
申请号：US17515523
申请日：2021-10-31
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
CPC classification number: G06N3/0635 , G06F7/5443 , G06N3/04
Abstract: An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3 × 3 × 64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.
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公开(公告)号：US20220382517A1
公开(公告)日：2022-12-01
申请号：US17335206
申请日：2021-06-01
Applicant: Redpine Signals, Inc.
Inventor： Martin KRAEMER , Ryan BOESCH , Wei XIONG
Abstract: A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values. The Gain Balanced AMAC has a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. In each of a series of multiply-accumulate cycles, the X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.
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公开(公告)号：US20220247425A1
公开(公告)日：2022-08-04
申请号：US17163493
申请日：2021-01-31
Applicant: Redpine Signals, Inc.
Inventor： Martin Kraemer , Ryan BOESCH , Wei XIONG
Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
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