公开(公告)号：US20100171219A1

公开(公告)日：2010-07-08

申请号：US12650805

申请日：2009-12-31

Applicant: David Moreau ,  Jerome Ciavatti

Inventor： David Moreau ,  Jerome Ciavatti

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect.

Abstract translation: 电介质层覆盖在半导体衬底上。 基板具有形成在其中的部件和适当的触点。 电介质层使衬底和组件与覆盖的导电互连层电绝缘。 阻挡层布置在介电层上方以将互连层与其它结构隔离。 然后在阻挡层上沉积铜层，实现具有第一宽度和第一高度的厚互连线。 然后，使用许多替代技术之一蚀刻阻挡层。 阻挡层具有第二宽度和第二高度，其中阻挡衬里的第二宽度被选择为大于厚铜互连的第一宽度。

公开(公告)号：US20100165963A1

公开(公告)日：2010-07-01

申请号：US12494122

申请日：2009-06-29

Applicant: Liwen Chu ,  George A. Vlantis

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W4/00 ,  H04L12/43

CPC classification number: H04W72/0446 ,  H04L12/43 ,  H04W72/005 ,  H04W74/04

Abstract: Methods and apparatus for implementing a robust unicast/broadcast/multicast protocol are provided. In one aspect, a method of avoiding collision of intra-basic service set unicast, broadcast or multicast transmissions notifies stations in the basic service set of a reserved transmit opportunity for a unicast, broadcast or multicast transmission. Transmissions from at least one station in the basic service set are deferred until after the reserved unicast, broadcast or multicast transmit opportunity.

Abstract translation: 提供了用于实现鲁棒的单播/广播/多播协议的方法和装置。 在一个方面，避免基本内部服务设置单播，广播或多播传输的冲突的方法通知用于单播，广播或多播传输的预留发送机会的基本服务集中的站。 基本服务集中的至少一个站的传输延迟到保留的单播，广播或多播发送机会之后。

公开(公告)号：US20100165527A1

公开(公告)日：2010-07-01

申请号：US12627729

申请日：2009-11-30

Applicant: Michael James Callahan, JR.

Inventor： Michael James Callahan, JR.

IPC: H02H3/00 ,  G01R31/08

CPC classification number: G01R19/16571 ,  H03K17/0826

Abstract: A bi-directional protection circuit employs a single comparator for detecting fault conditions. Diodes are coupled between a detection node and voltage dividers setting references for inverting and non-inverting comparator inputs, each diode forward biased during one of the positive and negative halves of the alternating current input signal cycle and coupling the detection node to a respective one of the inverting and non-inverting comparator inputs, and reverse biased during the other of the positive and negative halves and decoupling the detection node from the other of the inverting and non-inverting comparator inputs. Upon an overcurrent condition during the positive half, a voltage at the inverting comparator input is drawn above the reference voltage at the non-inverting input. Upon an overcurrent condition during the negative half, a voltage at the non-inverting comparator input is drawn below the reference voltage at the inverting input.

Abstract translation: 双向保护电路采用单个比较器来检测故障状况。 二极管耦合在检测节点和分压器之间，用于设置反相和非反相比较器输入的参考值，每个二极管在交流输入信号周期的正半周和负半周期期间正向偏置，并将检测节点耦合到 反相和非反相比较器输入，并在正半周和负半周中的另一个反向偏置，并将检测节点与反相和非反相比较器输入中的另一个去耦。 在正半周期的过电流条件下，反相比较器输入端的电压在非反相输入端上被吸引到基准电压之上。 在负半周期的过电流条件下，非反相比较器输入端的电压被拉低到反相输入端的参考电压以下。

公开(公告)号：US20100158272A1

公开(公告)日：2010-06-24

申请号：US12635548

申请日：2009-12-10

Applicant: Earl Corban Vickers

Inventor： Earl Corban Vickers

IPC: H03G5/00

CPC classification number: H03G3/00 ,  H04R3/04 ,  H04R5/04 ,  H04R2430/03

Abstract: Psychoacoustic bass audio signal enhancement can be accomplished using a monotonic, asymmetric polynomial distortion. A non-linear process applies a monotonic, asymmetric polynomial distortion function that has continuous first and second derivatives to generate even and odd harmonics of missing fundamental frequencies. This polynomial distortion produces the desired psychoacoustic effect with a fairly rapid roll-off so as to avoid unpleasant aliasing. Moreover, the lack of first-order discontinuities prevents clicks or glitches.

Abstract translation: 使用单调，非对称多项式失真可以实现心理声学低音音频信号增强。 非线性过程应用具有连续第一和第二导数的单调，非对称多项式失真函数，以产生缺失基频的均匀和奇次谐波。 这种多项式失真产生所需的心理声学效应，相当快速的滚降，以避免不愉快的混叠。 此外，缺乏一级不连续性可以防止点击或毛刺。

公开(公告)号：US07729077B2

公开(公告)日：2010-06-01

申请号：US11512466

申请日：2006-08-30

Applicant: Vineet Tiwari ,  Baris Posat

Inventor： Vineet Tiwari ,  Baris Posat

IPC: G11B5/02

CPC classification number: G11B5/02 ,  G11B5/022

Abstract: An H-bridge driver for a disk drive system includes first and second high side switched legs and first and second low side switched legs. An inductor head for writing data to and reading data from a magnetic media is connected to form a center of the H-bridge. The system includes a voltage regulator circuit that generates a common mode regulated voltage. First and second high side logic circuits, which selectively control operation of the first and second high side switched legs, are coupled between a high reference voltage and the common mode regulated voltage. First and second low side logic circuits, which control the first and second low side switched legs, are coupled between the common mode regulated voltage and ground.

Abstract translation: 用于磁盘驱动系统的H桥驱动器包括第一和第二高侧切换腿以及第一和第二低侧切换腿。 连接用于将数据写入磁性介质并从其读取数据的电感头，以形成H桥的中心。 该系统包括产生共模调节电压的电压调节器电路。 选择性地控制第一和第二高侧开关支路的操作的第一和第二高侧逻辑电路耦合在高参考电压和共模调节电压之间。 控制第一和第二低侧开关支路的第一和第二低端逻辑电路耦合在共模调节电压和地之间。

公开(公告)号：US20100130006A1

公开(公告)日：2010-05-27

申请号：US12698006

申请日：2010-02-01

Applicant: Ardeshir J. Sidhwa

Inventor： Ardeshir J. Sidhwa

IPC: H01L21/768

CPC classification number: C23C14/16 ,  C23C14/568 ,  C23C16/06 ,  C23C16/54 ,  H01L21/32051

Abstract: A thick metal layer is formed on a semiconductor integrated circuit in multiple different deposition chambers. A first portion of the metal layer is formed in a first deposition chamber, the first thickness being approximately half the target thickness. The substrate is then removed from the first chamber and transported to a second chamber. The deposition of the same metal layer continues in a second chamber, having the same grain structure and orientation. The second portion of the metal layer is grown to achieve the final thickness. By using two different deposition chambers to form the single metal layer, layers in excess of 25,000 angstroms in thickness can be obtained.

Abstract translation: 在多个不同的沉积室中的半导体集成电路上形成厚金属层。 金属层的第一部分形成在第一沉积室中，第一厚度大约是目标厚度的一半。 然后将基板从第一室移除并输送到第二室。 相同金属层的沉积在具有相同晶粒结构和取向的第二腔中继续。 生长金属层的第二部分以达到最终的厚度。 通过使用两个不同的沉积室来形成单个金属层，可以获得超过25,000埃厚度的层。

公开(公告)号：US07714746B2

公开(公告)日：2010-05-11

申请号：US11559588

申请日：2006-11-14

Applicant: Vincent Himpe

Inventor： Vincent Himpe

IPC: H03K17/94 ,  H03M11/00

CPC classification number: H03M11/20

Abstract: A key switch matrix circuit includes key switches arranged in rows and columns, each row having a scan line, each column having a sense line. Each key switch is operable to couple a scan line to a sense line. A scan signal delivery circuit supplies scan signals to the scan lines, the scan signals delivering a scan pulse to each row of the key switch matrix circuit in turn. A key switch detection circuit outputs a first signal if a key switch is operated and a scan pulse detection circuit outputs a second signal if a scan pulse is coupled to a sense line. The scan signal delivery circuit begins supplying scan signals in response to the first signal and stops supplying scan signals in response to the second signal. In one embodiment, a processor reads the sense lines in response to the second signal.

Abstract translation: 键开关矩阵电路包括以行和列布置的键开关，每行具有扫描线，每列具有感测线。 每个键开关可操作以将扫描线耦合到感测线。 扫描信号传送电路将扫描信号提供给扫描线，扫描信号依次将扫描脉冲传送给按键开关矩阵电路的每一行。 如果键开关被操作，键开关检测电路输出第一信号，并且如果扫描脉冲耦合到检测线，则扫描脉冲检测电路输出第二信号。 扫描信号传送电路响应于第一信号开始提供扫描信号，并且响应于第二信号停止提供扫描信号。 在一个实施例中，处理器响应于第二信号读取感测线。

公开(公告)号：US07714599B2

公开(公告)日：2010-05-11

申请号：US11615207

申请日：2006-12-22

Applicant: Riccardo Maggi ,  Massimo Scipioni

Inventor： Riccardo Maggi ,  Massimo Scipioni

IPC: G01R31/02

CPC classification number: G01R31/2856 ,  G01R31/2877

Abstract: An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.

Abstract translation: 集成电路老化测试系统包括集成电路和测试仪。 集成电路包括操作电路，用于加热操作电路的加热器和用于在加热时测试操作电路的老化测试电路。 封装包围操作电路，加热器和老化测试电路。 老化测试电路使操作电路工作并产生与之相关的数据。 测试仪从老化测试电路接收数据。 加热器可以被配置在封装内以加热操作电路的至少一个预定部分。

公开(公告)号：US20100109100A1

公开(公告)日：2010-05-06

申请号：US12686199

申请日：2010-01-12

Applicant: Frank Bryant ,  Murray Robinson

Inventor： Frank Bryant ,  Murray Robinson

IPC: H01L29/84

CPC classification number: B81C1/00119 ,  B81B2203/0315 ,  B81C2201/0109

Abstract: A microfabricated structure that includes a first layer of material on a substrate, and a second layer of material over the first layer that forms an encapsulated cavity, and a structural support layer added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

Abstract translation: 一种微制造结构，其包括在基底上的第一层材料，以及在形成封装空腔的第一层上的第二材料层，以及添加到第二层的结构支撑层。 可以在空腔中形成开口，并且空腔可以并排堆叠，通过开口垂直地堆叠有互连，并且两者的组合可以用于构造整个具有互连的堆叠阵列。

公开(公告)号：US07671571B2

公开(公告)日：2010-03-02

申请号：US12070710

申请日：2008-02-20

Applicant: Gary J. Burlak ,  Marian Mirowski

Inventor： Gary J. Burlak ,  Marian Mirowski

IPC: G05F1/575

CPC classification number: H02M1/32 ,  H02J1/00 ,  H02M3/157 ,  H02M2001/0012 ,  H03K17/0822 ,  H03K17/18 ,  H03K2017/0806

Abstract: A method includes receiving an activation signal at a semiconductor device and generating an output power signal at the semiconductor device in response to receiving the activation signal. The output power signal has a duty cycle. The method also includes providing the output power signal to a load. The output power signal provides power to the load. An amount of power provided to the load is based on the duty cycle of the output power signal. In addition, the method includes adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.

Abstract translation: 一种方法包括在半导体器件处接收激活信号，并响应于接收到激活信号在半导体器件处产生输出功率信号。 输出功率信号具有占空比。 该方法还包括向负载提供输出功率信号。 输出功率信号为负载提供电源。 提供给负载的功率量基于输出功率信号的占空比。 此外，该方法包括使用集成在半导体器件中的限流器和功率限制器中的至少一个来调节输出功率信号的占空比。