公开(公告)号：US07769988B1

公开(公告)日：2010-08-03

申请号：US09471877

申请日：1999-12-23

申请人： Adrian Sfarti ,  Korbin Van Dyke ,  Michael Frank ,  Arkadi Avrukin

发明人： Adrian Sfarti ,  Korbin Van Dyke ,  Michael Frank ,  Arkadi Avrukin

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F13/4027 ,  G06F2213/0038 ,  Y02D10/14 ,  Y02D10/151

摘要： A method of integrating a personal computing system and apparatus thereof include processing that begins by integrating a central processing unit with a North bridge on a single substrate such that the central processing unit is directly coupled to the North bridge via an internal bus. The processing then continues by providing memory access requests from the central processing unit to the North bridge at a rate of the central processing unit. The processing continues by having the North bridge buffer the memory access request and subsequently process the memory access requests at a rate of the memory. The method may be expanded by integrating a South bridge onto the same substrate as well as integrating system memory onto the same substrate.

摘要翻译： 集成个人计算系统及其装置的方法包括通过将中央处理单元与单个基板上的北桥集成开始的处理，使得中央处理单元经由内部总线直接耦合到北桥。 然后通过以中央处理单元的速率从中央处理单元向北桥提供存储器访问请求来继续处理。 通过使北桥缓冲存储器访问请求并随后以存储器的速率处理存储器访问请求，继续处理。 可以通过将南桥集成到相同的衬底上并将系统存储器集成到相同的衬底上来扩展该方法。

公开(公告)号：US20080049018A1

公开(公告)日：2008-02-28

申请号：US11778515

申请日：2007-07-16

申请人： Adrian Sfarti

发明人： Adrian Sfarti

IPC分类号： G06T17/20

CPC分类号： G06T17/20 ,  G06T17/30

摘要： The present invention provides a graphics processing unit for rendering objects from a software application executing on a processing unit in which the objects to be rendered are received as control points of bicubic surfaces. According to the method and system disclosed herein, the graphics processing unit includes a transform unit, a lighting unit, a renderer unit, and a tessellate unit for tessellating both rational and non-rational object surfaces in real-time.

摘要翻译： 本发明提供一种图形处理单元，用于从在要呈现的对象被接收的处理单元上执行的软件应用程序呈现对象，作为双三次表面的控制点。 根据本文公开的方法和系统，图形处理单元包括变换单元，照明单元，渲染单元和镶嵌单元，用于实时地分解理性和非理性物体表面。

公开(公告)号：US20070214255A1

公开(公告)日：2007-09-13

申请号：US11371507

申请日：2006-03-08

申请人： Mark Spitz ,  Adrian Sfarti

发明人： Mark Spitz ,  Adrian Sfarti

IPC分类号： G06F15/173

CPC分类号： H04L41/147 ,  G06F11/008 ,  H04L41/0803 ,  H04L41/085

摘要： A highly available multi-node computer system is operated by monitoring the aging and usage of a plurality of hardware components that are part of the system's networked nodes. While monitoring the components, a determination is made that one of the components has aged, worn, or both, to a level that is selected as being close enough to the component's predicted end of life in the system so as to prevent failure of the component in the system. A notification is sent to replace the component, in response to the determination. Other embodiments are also described and claimed.

摘要翻译： 通过监视作为系统网络节点的一部分的多个硬件组件的老化和使用来操作高度可用的多节点计算机系统。 在监视组件时，确定组件中的一个已经老化，磨损或两者都被选定为足够接近组件在系统中预测的使用寿命的水平，以防止组件的故障 在系统中。 响应于确定，发送通知以替换组件。 还描述和要求保护其他实施例。

公开(公告)号：US07190362B1

公开(公告)日：2007-03-13

申请号：US09009714

申请日：1998-01-20

申请人： Nicholas Baker ,  Mei-Chi Liu ,  Adrian Sfarti ,  Paolo Sabella

发明人： Nicholas Baker ,  Mei-Chi Liu ,  Adrian Sfarti ,  Paolo Sabella

IPC分类号： G06T15/00

CPC分类号： G06T1/60 ,  G06T1/20 ,  G06T15/005

摘要： A system and method for pipelining three-dimensional graphical data in which two-dimensional renderings of objects are created from polygon data by transforming and lighting each polygonal vertex and then connecting the vertices.

摘要翻译： 一种用于流水线三维图形数据的系统和方法，其中通过变换和点亮每个多边形顶点然后连接顶点，从多边形数据创建对象的二维渲染。

公开(公告)号：US6100898A

公开(公告)日：2000-08-08

申请号：US57171

申请日：1998-04-08

申请人： Adam Malamy ,  Nicholas R. Baker ,  Adrian Sfarti ,  Victor Tirva

发明人： Adam Malamy ,  Nicholas R. Baker ,  Adrian Sfarti ,  Victor Tirva

IPC分类号： G06T15/04 ,  G06T11/40

CPC分类号： G06T15/04

摘要： A system and method of selecting a level of detail in a texture-mapping system. Pixels are processed in a zig-zag traversal pattern to allow determination of vertical and horizontal change values in texture map coordinates. In this manner, accurate level of detail selection is achieved without unduly reducing efficiency or throughput of the graphics system.

摘要翻译： 在纹理映射系统中选择细节级别的系统和方法。 以Z字形遍历模式处理像素，以便确定纹理贴图坐标中的垂直和水平变化值。 以这种方式，在不会不当地降低图形系统的效率或吞吐量的情况下实现精确的细节选择水平。

公开(公告)号：US5581680A

公开(公告)日：1996-12-03

申请号：US132404

申请日：1993-10-06

申请人： Adrian Sfarti ,  Gunawan Ali-Santosa

发明人： Adrian Sfarti ,  Gunawan Ali-Santosa

IPC分类号： G06T11/00 ,  G09G5/20 ,  G09G5/393 ,  G06F15/00

CPC分类号： G09G5/393 ,  G06T11/001 ,  G09G5/20

摘要： A method and apparatus for drawing at least a two pixel wide antialiased line is described in which the apparatus utilizes an interpolator, having a set up unit and an iterator unit, and a blender. The set up unit determines various parameters of the line to be drawn and selects a pair of pixels adjacent to and straddling an idealized line representing the line to be drawn. The iterator unit determines the coverages of the pair of pixels based on the parameters output by the set up unit. The blender determines the color intensity values of the pair of pixels as a function of the coverages and writes the color values into a memory. The memory is a frame buffer type memory utilized to drive a display and is split into at least four banks so that the color values of the pair of pixels can be simultaneously stored in different memory banks. The apparatus also incorporates a method for resolving accumulation error in the derivation of each pixel's position and a method for accommodating for the effect of a third intersected pixel on the line to be drawn.

摘要翻译： 描述了用于绘制至少两个像素宽的抗锯齿线的方法和装置，其中该装置利用具有建立单元和迭代器单元的内插器和混合器。 设置单元确定要绘制的线的各种参数，并且选择与表示要绘制的线的理想线相邻并跨越的一对像素。 迭代器单元基于由设置单元输出的参数来确定该对像素的覆盖。 混合器根据覆盖率确定该对像素的颜色强度值，并将颜色值写入存储器。 存储器是用于驱动显示器并被分割成至少四个存储体的帧缓冲器型存储器，使得该对像素的颜色值可以同时存储在不同的存储体中。 该装置还包括一种用于分解每个像素位置的推导中的累积误差的方法以及用于在待绘制的线上适应第三相交像素的影响的方法。

公开(公告)号：US4941111A

公开(公告)日：1990-07-10

申请号：US853492

申请日：1986-04-18

申请人： Adrian Sfarti

发明人： Adrian Sfarti

IPC分类号： G06T11/80 ,  G06F3/033 ,  G06F3/048 ,  G06T15/30 ,  G09G5/393

CPC分类号： G06F3/04842 ,  G06T15/30 ,  G09G5/393

摘要： The picking method and apparatus comprise: A CPU and a direct memory access (DMA) circuit which is used with a graphics microprocessor (G.mu.P) for virtually redrawing a display list from a system memory of objects in a bit map. A starting address and a number corresponding to the number of instructions in a segment comprising a plurality of display lists are sent to the DMA for this purpose. When the coordinates of a pointer match the coordinates of a selected data object, a pick interrupt signal and special pick instruction is sent to the CPU. The CPU then uses the starting address of the display list of a selected object from a table to generate a new display list to perform a pre-selected operation on the selected data object. The clipping method and apparatus comprise a plurality of data planes for storing data objects, a match plane for storing a clipping object and a one-bit register. In use, the pixels in the data and match planes are scanned. When a match occurs between a pixel in the match plane and the contents of the one-bit register, a match signal is generated. The match signal enables the data planes to re-store the corresponding pixels of the data objects in the match planes.

公开(公告)号：US4901251A

公开(公告)日：1990-02-13

申请号：US847807

申请日：1986-04-03

申请人： Adrian Sfarti

发明人： Adrian Sfarti

IPC分类号： G06T11/00 ,  G06T11/40

CPC分类号： G06T11/40

摘要： A graphics co-processor that is autonomously responsive to an instruction for the filling of a complex polygon, as defined by an enumeration of P vertices is described. The co-processor preferably includes a micro-engine sequencer and ALU (arithmetic logic unit) for selecting a first vertex from the enumeration of P vertices and for decomposing the complex polygon into a set of P-2 triangles, wherein each triangle includes the first vertex and to successive vertices as presented in the enumeration of P vertices is derived. A sense value is derived for each of the resultant P-2 triangles and each triangle is filled with a predetermined fill quantity that is qualified by the respectively associated sense value of the triangle being filled. Thus, the present invention provides for the autonomous execution of a fill polygon instruction for polygons having such complexities as concavities, self-intersections, overlapping sections and "holes".

摘要翻译： 描述了自动响应于填充复数多边形的指令的图形协处理器，如由P顶点的枚举定义的。 协处理器优选地包括微引擎定序器和ALU（算术逻辑单元），用于从P顶点的枚举中选择第一顶点并将复数多边形分解为一组P-2三角形，其中每个三角形包括第一 导出顶点和连续顶点，如P顶点的枚举中所示。 对于每个所得到的P-2三角形导出感测值，并且每个三角形填充有由填充的三角形的分别相关联的感测值限定的预定填充量。 因此，本发明提供对具有凹凸，自相交，重叠部分和“孔”等复杂性的多边形的填充多边形指令的自主执行。

公开(公告)号：US4809169A

公开(公告)日：1989-02-28

申请号：US855224

申请日：1986-04-23

申请人： Adrian Sfarti ,  Achim Strupat

发明人： Adrian Sfarti ,  Achim Strupat

IPC分类号： G06F9/38 ,  G06F15/16 ,  G06F15/80

CPC分类号： G06F15/8007

摘要： A coprocessor architecture specifically adapted for parallel operation as one of an array of coprocessors is described. Each of the coprocessors of the array are commonly responsive to a host processor. The coprocessor architecture preferably includes a selector for enabling the responsiveness of the coprocessor architecture to instructions from the host processor including an enabled responsiveness unique among the plurality of coprocessors and enabled responsiveness that is in common with that of the plurality of the coprocessors. The coprocessor architecture further includes a microengine for qualifying the responsiveness of the coprocessor to instructions provided by the host processor including qualification of the enabled responsiveness of the coprocessor architecture as provided for by the selector. Consequently, the coprocessors of the array are readily managed both individually and, from the perspective of the host processor, as a single entity operating as a single instruction, multiple data machine. As such, the coprocessor array requires little, if any, managerial support from the host processor, regardless of the specific number of coprocessors participating in the coprocessor array.

摘要翻译： 描述了专门用于并行操作作为协处理器阵列之一的协处理器架构。 阵列的每个协处理器通常对主机处理器做出响应。 协处理器架构优选地包括选择器，用于使得协处理器架构对来自主机处理器的指令的响应能力包括在多个协处理器中唯一的启用的响应能力以及与多个协处理器的响应能力相同的响应能力。 协处理器架构还包括微引擎，用于将协处理器的响应能力用于由主机处理器提供的指令，包括由选择器提供的对协处理器架构的使能响应能力的鉴定。 因此，阵列的协处理器可以单独管理，并且从主机处理器的角度，作为单个实体操作为单个指令多数据机。 因此，无论协处理器参与协处理器阵列的具体数量如何，协处理器阵列都需要很少（如果有的话）来自主机处理器的管理支持。