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255 条记录 (耗时 0.022 秒)

    MEMS microphone and method of manufacturing the same
    33.
    发明授权
    MEMS microphone and method of manufacturing the same 有权

    公开(公告)号：US10993041B2

    公开(公告)日：2021-04-27

    申请号：US16056863

    申请日：2018-08-07

    申请人： DB HITEK CO., LTD.

    发明人： Jong Won Sun

    IPC分类号： H04R19/04 ,  B81B3/00 ,  B81C1/00 ,  H04R19/00 ,  H04R7/18 ,  H04R7/04 ,  H04R31/00

    摘要： A MEMS microphone includes a substrate having a cavity, a back plate being disposed over the substrate and having a plurality of acoustic holes, a diaphragm disposed between the substrate and the back plate, the diaphragm being spaced apart from the substrate and the back plate, covering the cavity to form an air gap between the back plate, and being configured to generate a displacement with responding to an acoustic pressure and a plurality of anchors extending from an end portion of the diaphragm to be integrally formed with the diaphragm, the anchors being arranged along a circumference of the diaphragm to be spaced apart from each other, and having lower surfaces making contact with an upper surface of the substrate to support the diaphragm. Thus, the MEMS microphone may have improved rigidity and flexibility.

    Output buffer circuit
    35.
    发明授权
    Output buffer circuit 有权

    公开(公告)号：US10886920B2

    公开(公告)日：2021-01-05

    申请号：US16814881

    申请日：2020-03-10

    申请人： DB HiTek Co., Ltd.

    发明人： Mun-Gyu Kim ,  Kyung-Tae Kim ,  Jae-Hong Ko

    IPC分类号： H03K5/12 ,  H03K19/0185 ,  G09G3/36

    摘要： An output buffer circuit is disclosed to achieve a high slew rate without increasing current consumption. The output buffer circuit includes an input circuit configured to output a first signal and a second signal in response to an input signal, and a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal to control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal.

    Display driver IC and display apparatus including the same
    36.
    发明授权
    Display driver IC and display apparatus including the same 有权

    公开(公告)号：US10777112B2

    公开(公告)日：2020-09-15

    申请号：US16424232

    申请日：2019-05-28

    申请人： DB HiTek Co., Ltd

    发明人： Jung Heo ,  Seung Jin Yeo ,  Jae Hong Ko ,  Hoon Sang Ryu ,  Woo Hyoung Seo

    IPC分类号： G09G3/20

    摘要： A display driver integrated circuit (DDI) includes a level shifter unit configured to convert a level of a control signal to a voltage in a range that equal to or greater than a first voltage and is equal to or less than a second voltage and output a switch control signal, and a voltage generator including a capacitor and a switch that is turned on or off based on or in response to the switch control signal and configured to generate at least one third voltage.

    SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    37.
    发明申请
    SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200279911A1

    公开(公告)日：2020-09-03

    申请号：US16804794

    申请日：2020-02-28

    申请人： DB HITEK CO., LTD.

    发明人： Young Seok Kim

    IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/423

    摘要： A super junction semiconductor device includes a substrate having a first conductive type, a blocking layer positioned on the substrate, the blocking layer including first conductive type pillars and second conductive type pillars, each extending in a vertical direction and arranging alternatively in a horizontal direction, and a gate structure disposed on the blocking layer, the gate structure extending in the horizontal direction and being electrically connected to ones of the first and second conductive type pillars. Thus, oscillation phenomena may be suppressed.

    Gamma correction circuit and gamma correction method
    38.
    发明授权
    Gamma correction circuit and gamma correction method 有权

    公开(公告)号：US10762825B2

    公开(公告)日：2020-09-01

    申请号：US16234313

    申请日：2018-12-27

    申请人： DB HiTek Co., Ltd.

    发明人： Kyoung-Tae Kim ,  Seung-Jin Yeo ,  Mun-Gyu Kim ,  Jae-Hong Ko

    IPC分类号： G09G3/20 ,  G09G3/3208 ,  G09G3/36

    摘要： Disclosed is a gamma correction circuit and method capable of minimizing power consumption by adding third and fourth input amplifiers receiving reference voltages which are identical to voltages to first and second input amplifiers, respectively, and deactivating the first and second input amplifiers during an always on display (AOD) mode. The gamma correction circuit includes a first input amplifier configured to output a maximum voltage when active, a second input amplifier configured to output a minimum voltage when active, a third input amplifier configured to output a highest gamma voltage in response to the first reference voltage, and a fourth input amplifier configured to output a lowest gamma voltage in response to the second reference voltage. The first and second input amplifiers are deactivated when the display driving device operates in the AOD mode.

    Method of manufacturing a gate structure for a nonvolatile memory device
    39.
    发明授权
    Method of manufacturing a gate structure for a nonvolatile memory device 有权

    公开(公告)号：US10756191B2

    公开(公告)日：2020-08-25

    申请号：US16265476

    申请日：2019-02-01

    申请人： DB HITEK CO., LTD.

    发明人： Sung Mo Gu ,  Sung Bok Ahn

    IPC分类号： H01L29/40 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423

    摘要： A method of manufacturing a gate structure for a nonvolatile memory device is disclosed. A tunneling oxide layer is formed on a substrate, and then a first polysilicon layer, a gate dielectric layer, a second polysilicon layer and a hard mask pattern are sequentially formed on the tunneling oxide layer. Then, the second polysilicon layer, the gate dielectric layer, and the first polysilicon layer are patterned through an etching process using the hard mask pattern to form stacked memory gates on the tunnel oxide layer, each including a floating gate, a gate dielectric layer pattern and a control gate on the tunneling oxide layer, and a select gate provided between the memory gates on the tunneling oxide layer.