公开(公告)号：US20120182863A1

公开(公告)日：2012-07-19

申请号：US13362319

申请日：2012-01-31

Applicant: Michel Ouellette ,  James Aweya ,  Delfin Y. Montuno ,  Kent Felske ,  Michael George Mayer

Inventor： Michel Ouellette ,  James Aweya ,  Delfin Y. Montuno ,  Kent Felske ,  Michael George Mayer

IPC: H04L12/44 ,  H04L12/26

CPC classification number: H04L41/12 ,  H04J3/0679

Abstract: In response to a network topology change, a clock root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.

Abstract translation: 响应于网络拓扑变化，时钟根节点通过构建时钟源拓扑树来为每个受影响的节点计算新的时钟路径，并且从该树中识别来自较高或相等层次的时钟源的网络节点的路径 到该网络节点。 根节点然后向每个节点发送一个网络消息，指示节点应该使用的新路径。 每个节点接收消息，并将新路径与现有路径进行比较。 如果路径不同，则节点获取刚刚在消息中接收到的新路径。 如果路径相同，则节点不执行任何操作并丢弃该消息。

公开(公告)号：US07656985B1

公开(公告)日：2010-02-02

申请号：US11279431

申请日：2006-04-12

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno ,  Kent Felske

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno ,  Kent Felske

IPC: H03D3/24

CPC classification number: H03L7/093 ,  H03L7/0992 ,  H03L7/18 ,  H04J3/0632 ,  H04J3/0664

Abstract: A timestamp-based all digital phase locked loop is utilized for clock synchronization for Circuit Emulation Service (“CES”) over packet networks. The all digital phase locked loop at a CES receiver includes a phase detector, a loop filter, a digital oscillator and a timestamp counter. The all digital phase locked loop enables the CES receiver to synchronize a local clock at the receiver with a clock at a CES transmitter, where indications of transmitter clock signals are communicated to the receiver as timestamps. The phase detector is operable to compute an error signal indicative of differences between the timestamps and a local clock signal. The loop filter is operable to reduce jitter and noise in the error signal, and thereby produce a control signal. The digital oscillator is operable to oscillate at a frequency based at least in-part on the control signal, and thereby produce a digital oscillator output signal. The timestamp counter operable to count pulses in the digital oscillator output signal, and output the local clock signal.

Abstract translation: 基于时间戳的全数字锁相环用于通过分组网络进行电路仿真服务（“CES”）的时钟同步。 CES接收机的全数字锁相环包括相位检测器，环路滤波器，数字振荡器和时间戳计数器。 全数字锁相环使得CES接收机能够使接收机处的本地时钟与CES发射机的时钟同步，其中发射机时钟信号的指示作为时间戳传送到接收机。 相位检测器可用于计算指示时间戳与本地时钟信号之间的差异的误差信号。 环路滤波器可操作以减少误差信号中的抖动和噪声，从而产生控制信号。 数字振荡器可操作以至少部分地基于控制信号以频率振荡，从而产生数字振荡器输出信号。 时间戳计数器可用于对数字振荡器输出信号中的脉冲进行计数，并输出本地时钟信号。

公开(公告)号：US07545804B2

公开(公告)日：2009-06-09

申请号：US10659320

申请日：2003-09-11

Applicant: Ernst A. Munter ,  Delfin Y. Montuno ,  James Aweya

Inventor： Ernst A. Munter ,  Delfin Y. Montuno ,  James Aweya

IPC: H04L12/54 ,  H04L12/56

CPC classification number: H04L49/103 ,  H04L49/1553

Abstract: A rotator switch including more tandem buffers than inputs is disclosed. An input data conditioner formats data to be transferred from the multiple inputs to the tandem buffers. Excess tandem buffers allow data to be transferred from inputs to tandem buffers at a rate less than the rate at which data arrives at the inputs. Excess capacity of the switch fabric may be used to carry overhead, or slow the rate at which data is transferred to the switch fabric.

Abstract translation: 公开了包括比输入更多的串联缓冲器的旋转开关。 输入数据调节器将要从多个输入传送到串联缓冲器的数据。 过多的串联缓冲器允许数据以低于数据到达输入的速率的速率从输入传输到串联缓冲器。 交换结构的过多容量可能用于携带开销，或者减慢数据传输到交换结构的速率。

公开(公告)号：US07424546B1

公开(公告)日：2008-09-09

申请号：US10426286

申请日：2003-04-30

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Montuno ,  Kent Felske

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Montuno ,  Kent Felske

IPC: G06F15/16 ,  G06F15/173 ,  G06F11/00

CPC classification number: H04L47/10 ,  H04L43/0894 ,  H04L43/16 ,  H04L47/12 ,  H04L47/193 ,  H04L47/31 ,  H04L47/32 ,  H04L69/02 ,  H04L69/28

Abstract: Disclosed is an Active Queue Management method and apparatus which uses traffic rate information for congestion control. Using a nonlinear fluid-flow model of Traffic Control Protocol, a proportional-integral controller in a closed loop configuration with gain settings characterized for stable operation allows a matching of the aggregate rate of the active TCP connections to the available capacity. Further disclosed is a method for calculation of the regime of gain settings for which stable operation of a given network obtains. This approach allows for capacity matching while maintaining minimal queue size and high link utilization.

Abstract translation: 公开了一种使用业务速率信息进行拥塞控制的活动队列管理方法和装置。 使用流量控制协议的非线性流体流模型，闭环配置中的比例积分控制器，其特征在于稳定操作的增益设置允许活动TCP连接的总速率与可用容量的匹配。 还公开了一种用于计算给定网络的稳定操作获得的增益设置的方案的方法。 这种方法允许容量匹配，同时保持最小的队列大小和高的链路利用率。

公开(公告)号：US07359324B1

公开(公告)日：2008-04-15

申请号：US10796321

申请日：2004-03-09

Applicant: Michel Ouellette ,  Delfin Montuno ,  James Aweya ,  Kent Felske

Inventor： Michel Ouellette ,  Delfin Montuno ,  James Aweya ,  Kent Felske

IPC: H04L12/26

CPC classification number: H04L43/087 ,  H04L43/0852

Abstract: A method for dynamically adjusting jitter buffer size according to buffer fill dynamics is disclosed. In one embodiment, an upper threshold and lower threshold for the jitter buffer are identified, wherein the lower buffer threshold identifies a minimum desirable number of packets in the jitter buffer, and the upper buffer threshold identifies a maximum desirable number of packets in the jitter buffer. Operating characteristics of the jitter buffer are monitored to identify instances when the jitter buffer size falls below or exceeds the desired thresholds. When a threshold is crossed, the adaptive algorithm alters the playback offset time, by introducing or deleting packets into the transmission path, to allow the jitter buffer size to return to a desirable target size within the threshold boundaries.

Abstract translation: 公开了一种根据缓冲区填充动态动态调整抖动缓冲区大小的方法。 在一个实施例中，识别抖动缓冲器的上阈值和下阈值，其中下缓冲器阈值标识抖动缓冲器中最小期望数量的分组，并且高缓冲器阈值识别抖动缓冲器中的最大期望数量的分组 。 当抖动缓冲区大小低于或超过所需阈值时，监视抖动缓冲区的操作特性以识别实例。 当超过阈值时，自适应算法通过将分组引入或删除到传输路径来改变播放偏移时间，以允许抖动缓冲器大小在阈值边界内返回到期望的目标大小。

公开(公告)号：US07336611B1

公开(公告)日：2008-02-26

申请号：US10633459

申请日：2003-08-01

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Montuno ,  Kent Felske

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Montuno ,  Kent Felske

IPC: H04J1/16

CPC classification number: H04L47/10 ,  H04L47/193 ,  H04L47/2408 ,  H04L47/263 ,  H04L47/31 ,  H04L47/32

Abstract: Disclosed is a rate-based multi-level Active Queue Management with drop precedence differentiation method and apparatus which uses traffic rate information for congestion control. Using a nonlinear fluid-flow model of Traffic Control Protocol, an integral controller in a closed-loop configuration with gain settings characterized for stable operation allows a matching of the aggregate rate of the active TCP connections to the available capacity. Further disclosed is a method for calculation of the regime of gains over which stable operation of a given network obtains. An enhancement of the basic algorithm provides the ability to drop low-precedence packets in preference to higher precedence packets. This approach allows for a rate-based AQM approach for application in a differentiated service environment.

Abstract translation: 公开了一种基于速率的多级活动队列管理，其具有使用流量信息进行拥塞控制的丢弃优先级分化方法和装置。 使用流量控制协议的非线性流体流模型，闭环配置的集成控制器具有以稳定操作为特征的增益设置，可以将活动TCP连接的总速率与可用容量进行匹配。 进一步公开的是一种用于计算给定网络获得的稳定运行的增益方案的方法。 基本算法的增强提供了优先级较低的优先级报文丢弃能力。 这种方法允许基于速率的AQM方法在差异化服务环境中应用。

公开(公告)号：US07286485B1

公开(公告)日：2007-10-23

申请号：US10680654

申请日：2003-10-07

Applicant: Michel Ouellette ,  James Aweya ,  Abel Dasylva ,  Delfin Montuno

Inventor： Michel Ouellette ,  James Aweya ,  Abel Dasylva ,  Delfin Montuno

IPC: H04J1/16 ,  H04J3/16 ,  H04L1/00 ,  H04L12/26 ,  H04L12/54

CPC classification number: H04L47/30 ,  H04L47/10 ,  H04L47/263 ,  H04L47/32

Abstract: Disclosed is a queue based multi-level Active Queue Management with drop precedence differentiation method and apparatus which uses queue size information for congestion control. The method provides for a lower complexity in parameter configuration and greater ease of configuration over a wide range of network conditions. A key advantage is a greater ability to maintain stabilized network queues, thereby minimizing the occurrences of queue overflows and underflows, and providing high system utilization.

Abstract translation: 公开了一种基于队列的多级活动队列管理，具有使用队列大小信息进行拥塞控制的丢弃优先级微分方法和装置。 该方法提供了参数配置的较低复杂度，并且在广泛的网络条件下更易于配置。 一个关键的优点是维持稳定的网络队列的更大能力，从而最大限度地减少队列溢出和下溢的发生，并提供高系统利用率。

公开(公告)号：US07043651B2

公开(公告)日：2006-05-09

申请号：US10076415

申请日：2002-02-19

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno ,  Kent E. Felske

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno ,  Kent E. Felske

IPC: G06F1/12 ,  H04L7/00

CPC classification number: H04N21/64322 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/18 ,  H04J3/0632 ,  H04J3/0664 ,  H04N21/242 ,  H04N21/4305

Abstract: A technique for synchronizing clocks in a network is disclosed. In one exemplary embodiment, the technique may be realized as a method for synchronizing clocks in a network. The method comprises receiving a first timestamp and a second timestamp, each indicating a respective time instance as determined by a first clock signal within the network. The method also comprises measuring a first time interval between the first timestamp and the second timestamp. The method further comprises generating a difference signal representing a difference between the first time interval and a second time interval, and generating a second clock signal based upon the difference signal such that the second clock signal is synchronized with the first clock signal.

公开(公告)号：US06993025B1

公开(公告)日：2006-01-31

申请号：US09475308

申请日：1999-12-30

Applicant: Delfin Y. Montuno ,  James Aweya

Inventor： Delfin Y. Montuno ,  James Aweya

IPC: H04L12/28

CPC classification number: H04L45/00 ,  H04L45/54 ,  Y10S707/99933

Abstract: A method of encoding a plurality of pre-defined codes into a search key and a method of using the search key to locate a longest matching pre-defined code to a given code is disclosed. Encoding the pre-defined codes into a search key involves producing a prefix node bit array (PNBA) having a plurality of bit positions corresponding to possible bit combinations of a bit string having a length equal to or less than the longest predefined code in said plurality of said pre-defined codes such that said bit positions are arranged by the lengths of said possible bit combinations and by numeric value of said possible bit combinations and to setting bits active in bit positions which correspond to bit combinations identified by said pre-defined codes. The method of locating involves producing a search mask encoding at least one portion of said given code and comparing said search mask to a search key having a Prefix Node Bit Array (PNBA) in which a bit is set active in at least one of a plurality of bit positions corresponding to possible bit combinations of bits in a bit string having a length equal to or less than the longest predefined code in said plurality of said pre-defined codes and arranged by the lengths of said possible bit combinations and by numeric values of said bit combinations, to identify a common active bit position in said search key and said search mask corresponding to a one of said pre-defined codes having a length greater than all others of said pre-defined codes which correspond to common active bit positions.

Abstract translation: 公开了一种将多个预定义代码编码成搜索关键字的方法，以及使用搜索关键字将最长匹配的预定义代码定位到给定代码的方法。 将预定义代码编码到搜索关键字中涉及产生具有多个比特位置的前缀节点比特阵列（PNBA），该多个比特位置对应于长度等于或小于所述多个中最长预定义码长度的比特串的可能比特组合 的所述预定义代码，使得所述位位置由所述可能位组合的长度和所述可能位组合的数值排列，并且设置位对应于由所述预定义代码识别的位组合的位位置中的位 。 定位方法涉及产生编码所述给定代码的至少一部分的搜索掩码，并将所述搜索掩码与具有前缀节点比特阵列（PNBA）的搜索关键字进行比较，其中将比特设置为多个 对应于具有等于或小于所述多个所述预定义代码中的最长预定义代码的长度的比特串中的比特的可能比特组合的比特位置，并且由所述可能比特组合的长度和数字值 所述比特组合，用于识别所述搜索关键字中的公共活动比特位置，并且所述搜索掩码对应于所述预定义码之一，其长度大于对应于公共活动比特位置的所述预定义码的所有其他长度。

公开(公告)号：US06928054B1

公开(公告)日：2005-08-09

申请号：US09665994

申请日：2000-09-20

Applicant: Delfin Y. Montuno ,  James Aweya ,  Michel Ouellette

Inventor： Delfin Y. Montuno ,  James Aweya ,  Michel Ouellette

IPC: H04L12/26 ,  H04L12/56 ,  H04L29/06

CPC classification number: H04L47/10 ,  H04L29/06 ,  H04L47/26 ,  H04L47/30 ,  H04L69/16 ,  H04L69/163

Abstract: An apparatus, method, computer-readable medium and signals for connection-class parameter control of packet flow, involves indicating a desired packet flow from a packet source to a network element having a queue, by communicating to the packet source an indication of a desired number of packets to be received from the source in a time period, in response to a class parameter associated with a class of connections supported by the network element and queue conditions at the network element.

Abstract translation: 用于分组流的连接级参数控制的装置，方法，计算机可读介质和信号涉及通过向分组源通信来指示期望的分组流从分组源到具有队列的网元， 响应于与网络元件支持的连接类相关联的类参数和网元处的队列条件，在时间段内从源接收的分组的数量。