公开(公告)号：US07535789B1

公开(公告)日：2009-05-19

申请号：US11528117

申请日：2006-09-27

Applicant: Thomas E. Fischaber ,  James M. Simkins ,  Peter H. Alfke

Inventor： Thomas E. Fischaber ,  James M. Simkins ,  Peter H. Alfke

IPC: G11C8/00

CPC classification number: G11C19/287 ,  G06F5/065 ,  G06F2205/066

Abstract: Circuits and methods of concatenating first-in-first-out memory circuits (FIFOs). A concatenated FIFO includes first and second FIFOs. The data output terminals of the first FIFO are coupled to the data input terminals of the second FIFO. The read clock of the second FIFO is the system read clock, and the write clock of the first FIFO is the system write clock. Communication between the first and second FIFOs is controlled by the faster of the two system clocks. A control circuit coupled to both the first and second FIFOs has a local clock input terminal coupled to the read clock input terminal of the first FIFO and the write clock input terminal of the second FIFO. The control circuit is driven by status signals from the first and second FIFOs, and generates a read enable signal for the first FIFO and a write enable signal for the second FIFO.

Abstract translation: 连接先进先出存储器电路（FIFO）的电路和方法。 级联FIFO包括第一和第二FIFO。 第一FIFO的数据输出端子耦合到第二FIFO的数据输入端。 第二个FIFO的读时钟是系统读时钟，第一个FIFO的写时钟是系统写时钟。 第一和第二FIFO之间的通信由两个系统时钟的更快控制。 耦合到第一和第二FIFO的控制电路具有耦合到第一FIFO的读时钟输入端和第二FIFO的写时钟输入端的本地时钟输入端。 控制电路由来自第一和第二FIFO的状态信号驱动，并产生第一FIFO的读使能信号和第二FIFO的写使能信号。

公开(公告)号：US07480690B2

公开(公告)日：2009-01-20

申请号：US11019854

申请日：2004-12-21

Applicant: James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

Inventor： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

IPC: G06F7/48

CPC classification number: G06F7/509

Abstract: Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

Abstract translation: 描述的是算术电路，逻辑上分为乘积发生器和加法器。 逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。 还可以控制复用电路以将多个外部添加的输入引导到加法器。 附加加数输入可以包括从其他算术电路级联的输入和输出。

公开(公告)号：US07467177B2

公开(公告)日：2008-12-16

申请号：US11019853

申请日：2004-12-21

Applicant: James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

Inventor： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

IPC: G06F7/38

CPC classification number: G06F7/49963

Abstract: Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

Abstract translation: 描述了执行灵活舍入方案的数学电路。 这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。 在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选择的舍入常数，计算校正因子，并将舍入常数，校正因子和 一个数据项以获得舍入的数据项。

公开(公告)号：US07233168B1

公开(公告)日：2007-06-19

申请号：US11151986

申请日：2005-06-14

Applicant: James M. Simkins

Inventor： James M. Simkins

IPC: G06F7/38

CPC classification number: G06F5/01

Abstract: Methods of setting and/or resetting a lookup table (LUT) programmable to operate in shift register mode. The LUT is configured to operate as a shift register, and the final bit of the shift register is implemented using a memory element associated with the LUT. The shift register is reset (or set) by applying a reset (set) signal to the memory element, while providing a low (high) value from the memory element to a shift-in input terminal of the LUT; and shifting the low (high) value through the bits of the shift register. To perform this task, a write enable signal is provided that is independent from the reset (set) signal of the memory element and enables a shift clock signal. The shift clock signal is then repeatedly toggled to shift the low (high) value from the memory element successively through each bit of the shift register, while the value stored in the memory element is held constant by means of the independent reset (set) signal.

Abstract translation: 设置和/或重置可编程以在移位寄存器模式下操作的查找表（LUT）的方法。 LUT被配置为作为移位寄存器操作，并且使用与LUT相关联的存储元件来实现移位寄存器的最后位。 通过向存储元件施加复位（置位）信号，同时从存储元件向LUT的移入输入端提供低（高）值来复位（或置位）移位寄存器; 并通过移位寄存器的位移动低（高）值。 为了执行该任务，提供独立于存储元件的复位（置位）信号的使能信号并使能移位时钟信号。 移位时钟信号然后被重复地切换，以通过移位寄存器的每个位置连续地从存储元件移位低（高）值，而存储在存储元件中的值通过独立复位（置位）信号保持不变 。

公开(公告)号：US06983394B1

公开(公告)日：2006-01-03

申请号：US10351033

申请日：2003-01-24

Applicant: Shawn K. Morrison ,  Andrew K. Percey ,  John D. Logue ,  James M. Simkins ,  Nicholas J. Sawyer

Inventor： Shawn K. Morrison ,  Andrew K. Percey ,  John D. Logue ,  James M. Simkins ,  Nicholas J. Sawyer

IPC: G06F1/04

CPC classification number: G06F1/10 ,  G01R31/31708 ,  G01R31/31725 ,  H04L7/0337

Abstract: Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.

Abstract translation: 描述了用于提供时钟信号的抖动和偏斜的量度的方法和装置。 时钟信号可以用作数字电路的输入。 在一个实施例中，数字延迟电路与处理电路结合使用，以连续测量输入时钟信号的抖动，从而随时间提供时钟信号性能测量。 在另一个实施例中，使用一对数字延迟电路来连续测量参考时钟信号和输入时钟信号之间的偏差或延迟，从而提供输入时钟信号随时间偏移的测量。 数字延迟电路形成在片上，因此可以提供抖动或偏斜的片上确定。

公开(公告)号：US06603368B1

公开(公告)日：2003-08-05

申请号：US10092865

申请日：2002-03-06

Applicant: Ronald S. Leahy ,  Randal R. Sylvester ,  James M. Simkins

Inventor： Ronald S. Leahy ,  Randal R. Sylvester ,  James M. Simkins

IPC: H03D300

CPC classification number: H04L27/38 ,  H04L7/0054

Abstract: A demodulator for demodulating clear mode waveforms such as Phase Shift Keyed and Quadrature Amplitude Modulated waveforms, is capable of demodulating signals with much greater data rates than the clock rate of the device in which the demodulator resides by converting serial input samples into vectors. The input vectors are converted to “soft-decision” (data estimate) vectors which are input to a parallel-to-serial multiplexer, and the vector elements are output serially at the symbol clock rate to represent demodulated data. In the preferred embodiment, the vector demodulator at least includes a preprocessor, a digital phase shifter, and a symbol demodulator which, inter alia, outputs a phase rotator command signal to control the carrier recover phase rotation process in the digital phase shifter. As a result, the maximum symbol rate—and hence the maximum data rate—is raised up to N times the device maximum clock rate for waveforms such as Biphase Shift Keying, where N represents the number of data elements in the vectors, and 2N for waveforms such as Quadrature Phase Shift Keyed. The data rate is increased by a factor of N for one sample per symbol, and by a factor of N/2 for 2 samples per symbol, etc.

Abstract translation: 用于解调诸如相移键控和正交幅度调制波形的清除模式波形的解调器能够通过将串行输入样本转换为向量来解调比解调器所在设备的时钟速率高得多的数据速率的信号。 将输入矢量转换为输入到并行到串行多路复用器的“软判决”（数据估计）向量，并且以符号时钟速率串行地输出向量元素以表示解调数据。 在优选实施例中，矢量解调器至少包括预处理器，数字移相器和符号解调器，其特别地，输出相位旋转器命令信号以控制数字移相器中的载波恢复相位旋转处理。 结果是，最大符号速率（因此最大数据速率）升高到诸如双相移键控等波形的器件最大时钟速率的N倍，其中N表示向量中的数据元素的数量，2N表示 波形如正交相移键控。 对于每个符号的一个样本，数据速率增加一个因子N，对于每个符号的2个样本等于N / 2的因子。