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    High data rate vector demodulator
    1.
    发明授权
    High data rate vector demodulator 有权
    高数据速率矢量解调器

    公开(公告)号：US06603368B1

    公开(公告)日：2003-08-05

    申请号：US10092865

    申请日：2002-03-06

    申请人： Ronald S. Leahy ,  Randal R. Sylvester ,  James M. Simkins

    发明人： Ronald S. Leahy ,  Randal R. Sylvester ,  James M. Simkins

    IPC分类号： H03D300

    CPC分类号： H04L27/38 ,  H04L7/0054

    摘要： A demodulator for demodulating clear mode waveforms such as Phase Shift Keyed and Quadrature Amplitude Modulated waveforms, is capable of demodulating signals with much greater data rates than the clock rate of the device in which the demodulator resides by converting serial input samples into vectors. The input vectors are converted to “soft-decision” (data estimate) vectors which are input to a parallel-to-serial multiplexer, and the vector elements are output serially at the symbol clock rate to represent demodulated data. In the preferred embodiment, the vector demodulator at least includes a preprocessor, a digital phase shifter, and a symbol demodulator which, inter alia, outputs a phase rotator command signal to control the carrier recover phase rotation process in the digital phase shifter. As a result, the maximum symbol rate—and hence the maximum data rate—is raised up to N times the device maximum clock rate for waveforms such as Biphase Shift Keying, where N represents the number of data elements in the vectors, and 2N for waveforms such as Quadrature Phase Shift Keyed. The data rate is increased by a factor of N for one sample per symbol, and by a factor of N/2 for 2 samples per symbol, etc.

    摘要翻译： 用于解调诸如相移键控和正交幅度调制波形的清除模式波形的解调器能够通过将串行输入样本转换为向量来解调比解调器所在设备的时钟速率高得多的数据速率的信号。 将输入矢量转换为输入到并行到串行多路复用器的“软判决”（数据估计）向量，并且以符号时钟速率串行地输出向量元素以表示解调数据。 在优选实施例中，矢量解调器至少包括预处理器，数字移相器和符号解调器，其特别地，输出相位旋转器命令信号以控制数字移相器中的载波恢复相位旋转处理。 结果是，最大符号速率（因此最大数据速率）升高到诸如双相移键控等波形的器件最大时钟速率的N倍，其中N表示向量中的数据元素的数量，2N表示 波形如正交相移键控。 对于每个符号的一个样本，数据速率增加一个因子N，对于每个符号的2个样本等于N / 2的因子。

    Applications of cascading DSP slices
    4.
    发明授权
    Applications of cascading DSP slices 有权
    级联DSP片的应用

    公开(公告)号：US07567997B2

    公开(公告)日：2009-07-28

    申请号：US11019518

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/48

    CPC分类号： G06F7/5443

    摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

    摘要翻译： 在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。 该IC允许实现一些基本的数学函数，例如加，减，乘和除。 可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

    Radio frequency data conveyance system including configurable integrated circuits
    5.
    发明授权
    Radio frequency data conveyance system including configurable integrated circuits 有权
    包括可配置集成电路的射频数据传送系统

    公开(公告)号：US07184466B1

    公开(公告)日：2007-02-27

    申请号：US10243411

    申请日：2002-09-12

    申请人： Brian K. Seemann ,  Brian T. Brunn ,  Normand T. Lemay, Jr. ,  Daniel J. Ferris, III ,  Thomas Anthony Lee ,  James M. Simkins ,  David B. Squires

    发明人： Brian K. Seemann ,  Brian T. Brunn ,  Normand T. Lemay, Jr. ,  Daniel J. Ferris, III ,  Thomas Anthony Lee ,  James M. Simkins ,  David B. Squires

    IPC分类号： H04B1/38

    CPC分类号： H04B1/406 ,  H04B1/0003

    摘要： A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.

    摘要翻译： 一种可在无线通信系统中的基站和/或终端用户设备中使用的数据传输集成系统。 集成系统包括第一和第二集成电路（IC）。 第一IC包括第一串并联（SERDES）模块，发射射频模块和接收射频模块。 发射和接收射频模块提供基站和终端用户设备之间的无线通信。 第二IC包括被编程为实现一个或多个无线通信功能的第二SERDES模块和可编程逻辑结构。 因此，可编程逻辑结构从提供给设备的数据（例如，视频，音频，控制或文本数据）生成出站数字信号，和/或处理入站数字信号以重新捕获原始传输的数据。 因此，可以容易地重新配置无线通信系统内的基站和/或终端用户设备。

    System and methods for reducing clock power in integrated circuits
    6.
    发明授权
    System and methods for reducing clock power in integrated circuits 有权
    集成电路中降低时钟功率的系统和方法

    公开(公告)号：US08104012B1

    公开(公告)日：2012-01-24

    申请号：US12363721

    申请日：2009-01-31

    申请人： Matthew H. Klein ,  Edward S. McGettigan ,  Stephen M. Trimberger ,  James M. Simkins ,  Brian D. Philofsky ,  Subodh Gupta

    发明人： Matthew H. Klein ,  Edward S. McGettigan ,  Stephen M. Trimberger ,  James M. Simkins ,  Brian D. Philofsky ,  Subodh Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F2217/62

    摘要： Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.

    摘要翻译： 在诸如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD）的可编程逻辑器件（PLD）中实现动态功率节省和资源的有效利用，通过接收指定包括时钟信号，时钟缓冲器的电路的设计网表 ，时钟使能信号和同步元件，检查设计网表以识别耦合到公共时钟和时钟使能信号的同步元件，将时钟信号切割到同步元件以形成修改后的设计网表，将门控时钟缓冲器插入修改的网表以输出 门控时钟信号到同步元件，响应于时钟使能信号，并在修改的网表上执行放置和布线。 提供了一种用于在EDA工具上执行该方法的系统。 可以将这些方法提供为存储在计算机可读介质上的可执行指令，其使可编程处理器执行该方法。

    Method and apparatus for virtual quad-port random access memory
    8.
    发明授权
    Method and apparatus for virtual quad-port random access memory 有权
    虚拟四端口随机存取存储器的方法和装置

    公开(公告)号：US07797610B1

    公开(公告)日：2010-09-14

    申请号：US11184310

    申请日：2005-07-19

    申请人： James M. Simkins

    发明人： James M. Simkins

    IPC分类号： G11C29/00

    CPC分类号： G11C8/16 ,  G11C29/52 ,  G11C2029/0409

    摘要： Embedded logic circuits in combination with a configurable logic resources on a common integrated circuit facilitates over-clocked operation of embedded, dual-port memory blocks. The implementation yields fully independent and simultaneous read/write access to the dual-port memory blocks from the configurable logic on each clock cycle of the configurable logic. Error detection/correction and data scrubbing is also facilitated by the embedded logic circuits, such that error detection/correction is completely transparent to the configurable logic, while data scrubbing is performed with minimal degradation to the memory access bandwidth of the configurable logic.

    摘要翻译： 嵌入式逻辑电路与公共集成电路上的可配置逻辑资源相结合，有助于嵌入式双端口存储器块的超时操作。 该实现在可配置逻辑的每个时钟周期上从可配置逻辑获得完全独立且同时的读/写访问双端口存储器块。 嵌入式逻辑电路也促进了错误检测/校正和数据擦除，使得错误检测/校正对于可配置逻辑完全透明，同时以可配置逻辑的存储器访问带宽的最小程度的降低来执行数据擦除。

    Method and apparatus for Viterbi synchronization
    9.
    发明授权
    Method and apparatus for Viterbi synchronization 有权
    维特比同步的方法和装置

    公开(公告)号：US07161995B1

    公开(公告)日：2007-01-09

    申请号：US10098282

    申请日：2002-03-15

    申请人： Raied N. Mazahreh ,  Edwin J. Hemphill ,  James M. Simkins

    发明人： Raied N. Mazahreh ,  Edwin J. Hemphill ,  James M. Simkins

    IPC分类号： H04B1/66

    CPC分类号： H03M13/41 ,  H04L1/0054

    摘要： Method and apparatus are described for determining when a convolution decoder is out of synchronization. Normalizations from a convolutional decoder are counted to provide a normalization count, and errors from the convolutional decoder are counted to provide an error count. One of the normalization count and the error count is compared to a first threshold associated with the selected one of the normalization count and the error count. The other of the normalization count and the error count is compared to a second threshold in response to meeting the first threshold, such as bit errors per X normalizations or normalizations per Y bit errors. From this latter comparison, an indicator is generated as to whether the convolutional decoder is synchronized or not.

    摘要翻译： 描述了用于确定卷积解码器何时不同步的方法和装置。 计数来自卷积解码器的归一化以提供归一化计数，并且对来自卷积解码器的错误进行计数以提供错误计数。 将归一化计数和错误计数之一与与所选归一化计数和错误计数中的一个相关联的第一阈值进行比较。 响应于满足第一阈值将归一化计数和错误计数中的另一个与第二阈值进行比较，例如每X标准化的位错误或每Y位错误的归一化。 根据后一种比较，产生关于卷积解码器是否同步的指示符。