公开(公告)号：US07362651B2

公开(公告)日：2008-04-22

申请号：US11383023

申请日：2006-05-12

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G11C8/00

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/1066

Abstract: A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.

Abstract translation: 双数据速率两同步动态随机存取（DDR2）存储器电路包括低速输入路径和通过输入耦合耦合到其上的高速输入路径并形成公共输入，公共输入耦合到存储器核心 存储器芯具有公共输出，其中高速输出路径和低速输出路径通过输出耦合耦合在一起并进一步耦合到存储器核心的公共输出端。