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    Resistance sensing for defeating microchip exploitation
    1.
    发明授权
    Resistance sensing for defeating microchip exploitation 失效
    用于击败微芯片开发的电阻感测

    公开(公告)号：US08214657B2

    公开(公告)日：2012-07-03

    申请号：US12181387

    申请日：2008-07-29

    申请人： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

    发明人： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

    IPC分类号： G06F11/30

    CPC分类号： G06F21/755 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

    摘要： A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

    摘要翻译： 一种方法，程序产品和装置包括位于安全敏感的微芯片电路附近的电阻结构。 可以检测抵抗结构的位置，构成或布置的变化，并启动防止逆向工程或其他开发工作的动作。 电阻结构可以自动和选择性地指定用于监测。 一些电阻结构可能具有不同的电阻率。 感测的电阻可以与期望的电阻，比率或其他电阻相关值进行比较。 结构可能与假结构混合，并且可以相对于彼此重叠或以其它方式布置，以进一步使不受欢迎的分析复杂化。

    Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures
    7.
    发明申请
    Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures 有权
    在DRAM架构寻址期间实施节能的结构和方法

    公开(公告)号：US20080232185A1

    公开(公告)日：2008-09-25

    申请号：US11688897

    申请日：2007-03-21

    申请人： Gerald K. Bartley ,  Darryl J. Becker ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

    发明人： Gerald K. Bartley ,  Darryl J. Becker ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

    IPC分类号： G11C5/14 ,  G11C8/08

    CPC分类号： G11C8/10 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

    摘要： A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.

    摘要翻译： 随机存取存储器件包括排列成行和列的各个存储器单元的阵列，每个存储器单元具有与其相关联的访问器件。 阵列的每行还包括与其相关联的多个N字线，其中N对应于阵列的独立可访问分区的数量，其中给定行中的每个访问设备仅耦合到N个字线中的一个 的行。 与阵列进行信号通信的地址解码器逻辑被配置为接收多个行地址位，并且对于由行地址位标识的所请求行，确定要请求行中的N个分区中的哪一个被访问， 未被激活的选定行内的设备，但不在要访问的分区内。

    Multi-Level Memory Architecture With Data Prioritization
    8.
    发明申请
    Multi-Level Memory Architecture With Data Prioritization 有权
    具有数据优先级的多级存储器架构

    公开(公告)号：US20080016297A1

    公开(公告)日：2008-01-17

    申请号：US11457234

    申请日：2006-07-13

    申请人： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

    发明人： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

    IPC分类号： G06F13/00

    CPC分类号： G06F13/161 ,  G06F12/08 ,  G06F12/122

    摘要： In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.

    摘要翻译： 在控制包括多个存储器位置的计算机可读存储器的方法中，确定存储在第一存储器位置中的数据单元的使用频率。 数据单元被移动到第二存储器位置，其不同于基于第二存储器位置的已知等待时间与数据单元的使用频率之间的对应关系而选择的第一存储器位置，其中第二存储器位置是 数据单元的主数据存储位置。