公开(公告)号：US20140033157A1

公开(公告)日：2014-01-30

申请号：US14043619

申请日：2013-10-01

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co., LTD.

Inventor： Fong-Yuan Chang ,  Wei-Shun Chuang ,  Sheng-Hsiung Chen ,  Hsian-Ho Chang ,  Ruey-Shi Rau

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A computer implemented method for routing a net includes generating, using one or more computer systems, a first wire associated with the net in accordance with data associated with the net including a multitude of pins and partitioning, using the one or more computer systems, the multitude of pins into at least a first group of pins in accordance with a first cost function. The method further includes connecting, using the one or more computer systems, a second wire associated with the first group of pins to the first wire, and connecting, using the one or more computer systems, a third wire from a pin of the first group of pins to the second wire.

Abstract translation: 用于路由网络的计算机实现的方法包括：使用一个或多个计算机系统，使用一个或多个计算机系统，根据与所述网络相关联的数据，使用一个或多个计算机系统来生成与所述网络相关联的第一线路，所述网络包括多个引脚和分区， 根据第一成本函数将多个引脚插入到至少第一组引脚中。 该方法还包括使用一个或多个计算机系统将与第一组引脚相关联的第二线连接到第一线，以及使用一个或多个计算机系统从第一组的引脚连接第三线 的针脚到第二根线。

公开(公告)号：US09286433B2

公开(公告)日：2016-03-15

申请号：US14082885

申请日：2013-11-18

Applicant: Synopsys Taiwan Co. Ltd. ,  Synopsys, Inc.

Inventor： Tung-Chieh Chen ,  Hung-Ming Chen ,  Yi-Peng Weng

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/06

Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.

Abstract translation: 提出了一种用于形成集成电路（IC）布局的计算机实现方法。 该方法包括当调用计算机以接收IC的第一布局并根据约束树生成IC的第二布局时，形成约束树。

公开(公告)号：US20150294055A1

公开(公告)日：2015-10-15

申请号：US14253784

申请日：2014-04-15

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co., Ltd.

Inventor： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/14

Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract translation: 用户的寄存器传输级别（RTL）设计进行分析和检测，以使感兴趣的信号得以保留，并且可以在合成后位于网表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网表中，以确保在运行时可以访问信号值。 之后，执行位置和路由（P＆R）处理，分析输出以将信号名称与寄存器（触发器和锁存器）或存储器块相关联，位置是现场可编程门阵列（FPGA）器件。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US20150089465A1

公开(公告)日：2015-03-26

申请号：US14496420

申请日：2014-09-25

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/06

Abstract: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.

Abstract translation: 提出了一种用于在电路设计中路由第一路径的计算机实现的方法。 该方法包括：当计算机被调用以在电路设计中路由第一路径时，通过向选择的先前构建的部分路径添加增量长度来迭代地构建多个部分路径来路由第一路径，所述添加按照 至少有第一个设计规则。 多个部分路径从第一个位置开始。 该方法还包括当多个部分路径在与第一位置不同的公共第二位置上结束时将多个部分路径中的每一个相互比较，并且节省导致最短的多个部分路径之一 第一条路。 该方法还包括消除未被选择以导致最短第一路径的多个部分路径之一。

公开(公告)号：US20150067632A1

公开(公告)日：2015-03-05

申请号：US14475276

申请日：2014-09-02

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Tung-Chieh CHEN ,  Po-Cheng Pan ,  Ching-Yu Chin ,  Hung-Ming Chen

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5081

Abstract: A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.

Abstract translation: 提出了一种计算机实现路由保存的方法。 该方法包括当计算机被调用来路由解决路径时，使用计算机分解第一模块，第二模块和源布局的路由路径之间的几何关系。 该方法还包括根据几何关系在计算机中布置解决方案布局中的路由路径。 解决方案布局不是通过源布局的缩放来定义的。

公开(公告)号：US20150007123A1

公开(公告)日：2015-01-01

申请号：US14486723

申请日：2014-09-15

Applicant: Synopsys Taiwan Co., LTD.

Inventor： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ration for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.

Abstract translation: 一种用于设计具有沿着第一和第二方向的尺寸并且包括至少第一块的集成电路（IC）的计算机实现的方法。 所述方法包括评估所述第一块的需求比，所述需求比反映了沿着所述第一方向的导电布线需求的比率和所述第二方向上的导电布线需求，当所述计算机被调用以评估所述需求比率时， 第一块。 该方法还包括根据需求比率创建一个或多个布线预约块。

公开(公告)号：US08875081B2

公开(公告)日：2014-10-28

申请号：US13778071

申请日：2013-02-26

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

Abstract translation: 描述了一种用于设计和制造集成电路的方法。 该方法使用线段的统计模型来精确估计块内最小长度正交线段的预期长度。 根据这些估计，该方法精确地估计所需的水平和垂直路由资源之间的比例，称为“H / V需求比”。从H / V需求比率来看，块的高度和宽度的准确估计可以是 决心。 此后，可以快速且准确地执行放置和布线，从而允许块被快速且成本有效地设计和制造。 还描述了一种设计具有有效的金属-1资源利用的集成电路的方法。

公开(公告)号：US08869084B2

公开(公告)日：2014-10-21

申请号：US13684496

申请日：2012-11-24

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Chien-Fu Chung ,  Yuan-Kai Pei ,  Shyh-An Tang

IPC: G06F17/50 ,  G06F11/22 ,  G06F9/455

CPC classification number: G06F17/5081

Abstract: A method for generating a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC) is disclosed. In the method, a model is defined, wherein the model comprises a plurality of parameters for generating a layout of the cell. Next an initial layout for the cell can be generated according to an initial set of values for the plurality of parameters. Then design rule checking (DRC) is performed for the initial layout based on a set of design rules. If any violations are found, the corresponding violation reports will be associated with the model. Therefore, a new set of values for the plurality of parameters can be generated by analyzing the violation reports collectively based on the model. With the new set of values for the plurality of parameters and above steps repeated, until no violation is found, a “DRC clean” layout can be generated.

Abstract translation: 公开了一种用于生成由设计规则检查（DRC）引导的集成电路（IC）的单元的布局的方法。 在该方法中，定义模型，其中模型包括用于生成小区布局的多个参数。 接下来，可以根据多个参数的初始值来生成单元的初始布局。 然后，基于一组设计规则，对初始布局执行设计规则检查（DRC）。 如果发现任何违规行为，相应的违规报告将与该模型相关联。 因此，可以通过基于模型集体分析违规报告来生成用于多个参数的新的一组值。 利用重复的多个参数和上述步骤的新的一组值，直到没有发现违规，可以生成“DRC清洁”布局。

公开(公告)号：US20140075402A1

公开(公告)日：2014-03-13

申请号：US14082885

申请日：2013-11-18

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co. Ltd.

Inventor： Tung-Chieh Chen ,  Hung-Ming Chen ,  Yi-Peng Weng

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/06

Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.

Abstract translation: 提出了一种用于形成集成电路（IC）布局的计算机实现方法。 该方法包括当调用计算机以接收IC的第一布局并根据约束树生成IC的第二布局时，形成约束树。

公开(公告)号：US20140013293A1

公开(公告)日：2014-01-09

申请号：US13718979

申请日：2012-12-18

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Chih-Neng Hsu ,  I-Liang Lin ,  Wen-Chi Feng

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: Power information associated with an IC design is displayed graphically and hierarchically using a power map, thereby providing an intuitive way for describing the power distribution among various power domains of the IC and parent-child relationships within the power domains. Each power domain is associated with a power control for controlling the power domain. The status of the power control for each power domain is displayed on the power map. The power map may include a token to set and display current operating mode of the IC design to enable the IC design to be debugged under different operating modes.

Abstract translation: 与IC设计相关联的功率信息使用功率图图形和分层显示，从而提供用于描述IC的各个功率域和功率域内的父子关系之间的功率分布的直观方式。 每个功率域与用于控制功率域的功率控制相关联。 每个电源域的电源控制状态显示在电源图上。 功率图可以包括用于设置和显示IC设计的当前操作模式的令牌，以使IC设计能够在不同的操作模式下进行调试。