公开(公告)号：US09256706B2

公开(公告)日：2016-02-09

申请号：US14476320

申请日：2014-09-03

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Tung-Chieh Chen ,  Po-Hsun Wu ,  Po-Hung Lin ,  Tsung-Yi Ho

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5063 ,  G06F17/5072 ,  G06F17/5081

Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.

Abstract translation: 用于生成设计布局的计算机实现的方法包括调用计算机以接收设计的示意图，生成与设计相关联的连接图，将连接图与存储在数据库中的多个连接图进行比较，并选择 在生成设计布局时与匹配连接图相关联的布局。

公开(公告)号：US20150143322A1

公开(公告)日：2015-05-21

申请号：US14541359

申请日：2014-11-14

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Jui-Hsiang Liu ,  Hsin-I Lin ,  Tung-Chieh Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.

Abstract translation: 设计师使用选项设备在原理图设计中切换一个或多个信号流，以为相同的设计创建不同的版本。 目前，没有相关的自动放置选项设备的自动工具。 在各种实施例中，使用选项设备实例来决定选项设备位置。 选项设备可以自动放置，并根据需要考虑和调整路由。

公开(公告)号：US08943452B2

公开(公告)日：2015-01-27

申请号：US13720737

申请日：2012-12-19

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Chih-Neng Hsu ,  I-Liang Lin ,  Wen-Chi Feng

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract translation: 一种计算机实现的方法，用于通过将功率规格格式表示的功率规格及其相应的电路设计集成在称为功率图的电源原理图中来调试IC设计的功率方面。 功率图是通过使用通过将原始电路设计层次重新分组到由电力规范定义的新层次来生成的电力数据库来创建的。 功率图包含功率单元符号（如隔离单元，电平转换器，电源开关）和信号网，并可显示电源域之间的关系。 电源图还可以在连接电源域的信号之间显示电源规格和电路设计之间的不匹配或错误。 此外，功率图可以与模拟结果一起使用。

公开(公告)号：US08893069B2

公开(公告)日：2014-11-18

申请号：US13646664

申请日：2012-10-06

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Yu-Chi Su ,  Ming-I Lai ,  Hsiao-Tzu Lu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5063

Abstract: A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively.

Abstract translation: 公开了一种基于拓扑比较策略的通过识别具有相同或相似示意图结构的子电路的布局图案或布局约束重用的计算机实现的方法。 所选择的子电路被转换为表示所选子电路的实例之间的相对位置的拓扑。 基于拓扑，识别并识别在原理图的预定义范围内具有相同或相似拓扑的一个或多个子电路。 因此，所选择的子电路的布局或布局约束被复制并与每个所识别的子电路相关联。 此外，一旦子电路被识别，它们可以被列在具有符号的用户界面上，以允许用户分别确认每个所识别的子电路。

公开(公告)号：US08719762B2

公开(公告)日：2014-05-06

申请号：US13730543

申请日：2012-12-28

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F8/20

Abstract: A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design.

Abstract translation: 集成定制原型板和控制器以形成用于仿真电路设计的仿真系统。 控制器可以设置在适配器板上。 定制原型板由一组板描述文件定义，进一步定义了系统中使用的FPGA器件，以及定制原型板上的FPGA器件和连接器之间的导线连接。 FPGA器件根据分区电路设计进行配置。 FPGA器件中的每个分割电路与用于与控制器通信以控制和探测仿真的验证模块相关联。 主机工作站可以用于与控制器链接以支持电路设计的协同仿真或协同仿真。

公开(公告)号：US20130305207A1

公开(公告)日：2013-11-14

申请号：US13891062

申请日：2013-05-09

Applicant: SYNOPSYS, INC. ,  SYNOPSYS TAIWAN CO. LTD.

Inventor： Ming Han Hsieh ,  Chih-Neng Hsu ,  Ming-Hui Hsieh

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/78

Abstract: A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window.

Abstract translation: 一种用于检测低功率IC模拟中的信号行为异常的方法，包括接收IC的电路设计和功率规格，根据功率规格确定至少一个功率序列检验规则，模拟电路设计和功率规格 以获得转储文件，基于所述转储文件识别所述至少一个功率序列检查规则的至少一个异常，以及生成与所识别的所述至少一个功率序列检查规则的异常相关的信息。 该方法还包括通过在波​​形窗口中显示与异常相关联的不正常信号的波形以及电路设计的一部分和/或与该异常相关联的功率规范的一部分来设置调试器中的上下文以调试异常 在文本窗口中出现异常。

公开(公告)号：US10068040B2

公开(公告)日：2018-09-04

申请号：US14791216

申请日：2015-07-02

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Yung Chuan Chen ,  I-Liang Lin ,  Li-Chi Chang ,  Bindesh Patel

IPC: G06F17/50 ,  G06F11/36

Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

公开(公告)号：US09449138B2

公开(公告)日：2016-09-20

申请号：US14452368

申请日：2014-08-05

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.

Abstract translation: 提出了一种仿真电路设计的系统。 该系统包括通过仿真接口耦合到现场可编程门阵列（FPGA）的主机工作站，其被配置为当主机工作站被调用以验证电路设计时仿真和验证电路设计。 仿真接口被配置为提供用于至少验证的定时和控制信息。 该系统进一步包括非暂时性的计算机可读存储介质，其包括指令，当执行时，使得计算机编译电路设计的一部分以及适于配置FPGA的相关联的验证模块。 根据描述文件执行编译。

公开(公告)号：US09311441B2

公开(公告)日：2016-04-12

申请号：US14541359

申请日：2014-11-14

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Jui-Hsiang Liu ,  Hsin-I Lin ,  Tung-Chieh Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.

Abstract translation: 设计师使用选项设备在原理图设计中切换一个或多个信号流，以为相同的设计创建不同的版本。 目前，没有相关的自动放置选项设备的自动工具。 在各种实施例中，使用选项设备实例来决定选项设备位置。 选项设备可以自动放置，并根据需要考虑和调整路由。

公开(公告)号：US08924912B2

公开(公告)日：2014-12-30

申请号：US13954783

申请日：2013-07-30

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co., Ltd.

Inventor： Chia-Ling Ho ,  Jian-Cheng Lin ,  Jencheng Wang

IPC: G06F17/50 ,  G06F11/36

CPC classification number: G06F17/5022 ,  G06F11/362 ,  G06F11/3636 ,  G06F17/5009

Abstract: A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace as execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call frames. Furthermore, users can debug the testbench code utilizing a virtual simulation, which is done by post-processing records of the virtual simulation stored in a database.

Abstract translation: 一种计算机实现的方法，用于通过记录呼叫帧的跟踪以及电路设计的活动来调试与电路设计相关联的测试台的测试台代码。 通过关联和显示记录的调用帧轨迹，该方法使用户能够轻松跟踪由测试台执行的子程序的执行历史，从而调试测试平台代码。 此外，用户可以通过使用记录的调用帧跟踪来跟踪测试平台代码的源代码。 此外，用户可以使用虚拟仿真来调试测试平台代码，虚拟仿真是通过后处理存储在数据库中的虚拟仿真的记录完成的。