公开(公告)号：US10228951B1

公开(公告)日：2019-03-12

申请号：US14831661

申请日：2015-08-20

Applicant: Apple Inc.

Inventor： Kulin N. Kothari ,  Mridul Agarwal ,  Pradeep Kanapathipillai

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for committing store instructions out of order from a store queue are described. A processor may store a first store instruction and a second store instruction in the store queue, wherein the first store instruction is older than the second store instruction. In response to determining the second store instruction is ready to commit to the memory hierarchy, the processor may allow the second store instruction to commit before the first store instruction, in response to determining that all store instructions in the store queue older than the second store instruction are non-speculative. However, if it is determined that at least one store instruction in the store queue older than the second store instruction is speculative, the processor may prevent the second store instruction from committing to the memory hierarchy before the first store instruction.

公开(公告)号：US09501284B2

公开(公告)日：2016-11-22

申请号：US14502901

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Pradeep Kanapathipillai ,  Richard F. Russo ,  Sandeep Gupta ,  Conrado Blasco

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

Abstract: A processor includes a mechanism that checks for and flushes only speculative loads and any respective dependent instructions that are younger than an executed wait for event (WEV) instruction, and which also match an address of a store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor. The mechanism may allow speculative loads that do not match the address of any store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor.

Abstract translation: 处理器包括一种机制，其仅检查和刷新推测负载以及比执行的等待事件（WEV）指令更年轻的任何相应的依赖指令，并且还匹配已经被确定已被执行的存储指令的地址 在由不同处理器执行配对SEV指令之前由不同的处理器。 该机制可以允许在由不同的处理器执行配对的SEV指令之前，已经确定已被不同处理器执行的任何存储指令的地址不匹配的推测性负载。

公开(公告)号：US09383995B2

公开(公告)日：2016-07-05

申请号：US13750972

申请日：2013-01-25

Applicant: Apple Inc.

Inventor： Pradeep Kanapathipillai ,  Hari Kannan ,  Po-Yung Chang ,  Ming-Ta Hsu ,  Rajat Goel

IPC: G06F9/30 ,  G06F13/00 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3834

Abstract: Techniques are disclosed relating to ordering of load instructions in a weakly-ordered memory model. In one embodiment, a processor includes a cache with multiple cache lines and a store queue configured to maintain status information associated with a store instruction that targets a location in one of the cache lines. In this embodiment, the processor is configured to set an indicator in the status information in response to migration of the targeted cache line. The indicator may be usable to sequence performance of load instructions that are younger than the store instruction. For example, the processor may be configured to wait, based on the indicator, to perform a younger load instruction that targets the same location as the store instruction until the store instruction is removed from the store queue. This may prevent forwarding of the value of the store instruction to the younger load and preserve load-load ordering.

Abstract translation: 公开了关于弱有序存储器模型中的加载指令的排序的技术。 在一个实施例中，处理器包括具有多个高速缓存行的高速缓存和存储队列，该存储队列被配置为维护与存储指令相关联的状态信息，所述存储指令针对高速缓存行之一中的位置 在该实施例中，处理器被配置为响应于目标高速缓存线的迁移而将状态信息中的指示符设置成。 该指示符可用于对比小于存储指令的加载指令的性能进行排序。 例如，处理器可以被配置为基于指示符等待执行与存储指令相同的位置的较年轻的加载指令，直到存储指令从存储队列中移除。 这可能会阻止将存储指令的值转发到较小的负载并保持负载负载顺序。

公开(公告)号：US09229866B2

公开(公告)日：2016-01-05

申请号：US14089014

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Hari S. Kannan ,  Brian P. Lilly ,  Perumal R. Subramoniam ,  Pradeep Kanapathipillai

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0842 ,  G06F12/0857 ,  G06F12/0888

Abstract: Systems, methods, and apparatuses for reducing writes to the data array of a cache. A cache hierarchy includes one or more L1 caches and a L2 cache inclusive of the L2 cache(s). When a request from the L1 cache misses in the L2 cache, the L2 cache sends a fill request to memory. When the fill data returns from memory, the L2 cache delays writing the fill data to its data array. Instead, this cache line is written to the L1 cache and a clean-evict bit corresponding to the cache line is set in the L1 cache. When the L1 cache evicts this cache line, the L1 cache will write back the cache line to the L2 cache even if the cache line has not been modified.

Abstract translation: 用于减少对缓存的数据阵列的写入的系统，方法和装置。 高速缓存层级包括一个或多个L1高速缓存和包括L2高速缓存的L2高速缓存。 当来自L1缓存的请求在L2高速缓存中丢失时，L2缓存向存储器发送填充请求。 当填充数据从存储器返回时，L2缓存延迟将填充数据写入其数据阵列。 相反，该缓存行被写入到L1高速缓存中，并且在高速缓存中设置与高速缓存行相对应的清除位。 当L1高速缓存驱逐此高速缓存行时，即使高速缓存行未被修改，L1高速缓存也将高速缓存行写回到L2高速缓存。

公开(公告)号：US20140181403A1

公开(公告)日：2014-06-26

申请号：US13725066

申请日：2012-12-21

Applicant: APPLE INC.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Perumal R. Subramoniam ,  Pradeep Kanapathipillai

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/0888

Abstract: Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the cache hierarchy. If an uncacheable load misses in the L2 cache, then allocation of the uncacheable load will be restricted to a subset of the ways of the L2 cache. If an uncacheable store memory operation hits in the L1 cache, then the hit cache line can be updated with the data from the memory operation. If the uncacheable store misses in the L1 cache, then the uncacheable store is sent to a core interface unit.Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.

Abstract translation: 用于保持不可缓存的数据一致的系统，处理器和方法。 处理器包括多级缓存层次结构，并且不可缓存的加载存储器操作可以在高速缓存层级的任何级别缓存。 如果L2缓存中存在不可缓存的加载错误，则不可缓存的加载的分配将被限制为L2高速缓存的一部分。 如果不可缓存的存储器操作命中在L1缓存中，则命中高速缓存行可以用来自存储器操作的数据来更新。 如果不可缓存的商店在L1缓存中丢失，则不可缓存的商店被发送到核心接口单元。 在发送到L2缓存之前，多个连续的存储器缺失在核心接口单元中被合并到更大的数据块中。