公开(公告)号：US20200081717A1

公开(公告)日：2020-03-12

申请号：US16541507

申请日：2019-08-15

Applicant: Arm Limited

Inventor： Luc ORION ,  Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Eddy LAPEYRE

IPC: G06F9/38

Abstract: Branch prediction circuitry comprises: a return address prediction structure to store at least one predicted return address; and a branch target buffer (BTB) structure comprising entries each for specifying predicted branch information for a corresponding block of instructions. Within at least a subset of entries of the BTB structure, each entry specifies the predicted branch information with an encoding incapable of simultaneously indicating both: that the corresponding block of instructions is predicted to include a return branch instruction (for which the return address prediction structure is used to predict the target address); and the predicted target address for the return branch instruction. This can provide a more efficient BTB structure which requires less circuit area and power for a given level of branch prediction performance.

公开(公告)号：US20200065105A1

公开(公告)日：2020-02-27

申请号：US16108115

申请日：2018-08-22

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Eddy LAPEYRE ,  Luc ORION

IPC: G06F9/38

Abstract: An apparatus and method are provided for detecting regularity in a number of occurrences of an event observed during multiple instances of a counting period. The apparatus has regularity detection circuitry for seeking to detect such a regularity, and a storage providing a storage entry having a count value field to store a count value and a confidence indication field to indicate a confidence in the regularity. The regularity detection circuitry is arranged to consider the multiple instances of the counting period in pairs, for one instance in the pair the regularity detection circuitry incrementing the count value following each occurrence of the event, and for the other instance in the pair the regularity detection circuitry decrementing the count value following each occurrence of the event. Check circuitry is then arranged, following completion of both counting periods in the pair, to adjust the confidence indication to indicate an increased confidence when it is determined that the count value has returned to an initial value, and otherwise to adjust the confidence indication to indicate a decreased confidence and to reset the count value to the initial value. Such an approach provides a particularly storage efficient mechanism for seeking to detect regularity in a number of occurrences of an event.

公开(公告)号：US20200050458A1

公开(公告)日：2020-02-13

申请号：US16100344

申请日：2018-08-10

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Luc ORION ,  Guillaume BOLBENES ,  Eddy LAPEYRE

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry to execute instructions, and branch prediction circuitry for making branch outcome predictions in respect of branch instructions. The branch prediction circuitry includes loop minimum iteration prediction circuitry having one or more entries, where each entry is associated with a loop controlling branch instruction that controls repeated execution of a loop comprising a number of instructions. During a training phase for an entry, the loop minimum iteration prediction circuitry seeks to identify a minimum number of iterations of the loop. The loop minimum iteration prediction circuitry is then arranged, when the training phase has successfully identified a minimum number of iterations, to subsequently identify a branch outcome prediction for the associated loop controlling branch instruction for use during the minimum number of iterations. It has been found that such an approach can significantly improve prediction accuracy for loop controlling branch instructions associated with loops that do not have a stable total number of iterations.

公开(公告)号：US20190196833A1

公开(公告)日：2019-06-27

申请号：US15852065

申请日：2017-12-22

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Vincenzo CONSALES ,  Eddy LAPEYRE

IPC: G06F9/38 ,  G06F9/30

Abstract: Data processing circuitry comprises fetch circuitry to fetch blocks, containing instructions for execution, defined by a fetch queue; and prediction circuitry to predict one or more next blocks to be fetched and to add the predicted next blocks to the fetch queue; the prediction circuitry comprising: branch prediction circuitry to detect a predicted branch destination for a branch instruction in a current block, the predicted branch destination representing either a branch target for a branch predicted to be taken or a next instruction after the branch instruction, for a branch predicted not to be taken; and sequence prediction circuitry to detect sequence data, associated with the predicted branch destination, identifying a next block following the predicted branch destination in the program flow order having a next instance of a branch instruction, to add to the fetch queue the identified next block and any intervening blocks between the current block and the identified next block, and to initiate branch prediction in respect of the predicted next instance of a branch instruction.

公开(公告)号：US20160306632A1

公开(公告)日：2016-10-20

申请号：US14690603

申请日：2015-04-20

Applicant: ARM LIMITED

Inventor： Houdhaifa BOUZGUARROU

IPC: G06F9/38

CPC classification number: G06F9/3848

Abstract: A tagged geometric length (TAGE) branch predictor 16 incorporates multiple prediction tables 20, 22, 24, 26. Each of these prediction tables has prediction storage lines which store a common stored TAG value 50 and a plurality of branch predictions 52, 54 in respect of different offset positions within a block of program instructions read in parallel. Each of the branch prediction has an associated validity indicator 56, 58. Update of predictions stored may be made by a partial allocation mechanism in which a TAG match occurs and a branch storage line is partially overwritten or by full allocation in which no already matching TAG victim storage line can be identified and instead a whole prediction storage line is cleared and the new prediction stored therein.

Abstract translation: 标记的几何长度（TAGE）分支预测器16并入多个预测表20,22,24,26。这些预测表中的每一个具有预测存储线，其存储公用存储的TAG值50和多个分支预测52,54 在并行读取的程序指令块内的不同偏移位置。 分支预测中的每一个具有相关联的有效性指示符56,58。可以通过部分分配机制来进行更新所存储的预测，其中发生TAG匹配并且分支存储线被部分覆盖，或者通过完全分配来完成，其中没有已经匹配的TAG 可以识别受害者存储线，而是清除整个预测存储线，并存储新的预测。