公开(公告)号：US11682432B2

公开(公告)日：2023-06-20

申请号：US17343829

申请日：2021-06-10

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Saurabh Pijuskumar Sinha ,  Shidhartha Das ,  Mudit Bhargava ,  Rahul Mathur

IPC: G11C5/14 ,  G11C5/02

CPC classification number: G11C5/147 ,  G11C5/02

Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.

公开(公告)号：US20230029860A1

公开(公告)日：2023-02-02

申请号：US17388927

申请日：2021-07-29

Applicant: Arm Limited

Inventor： Joshua Randall ,  Alejandro Rico Carro ,  Dam Sunwoo ,  Saurabh Pijuskumar Sinha ,  Jamshed Jalal

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0813 ,  H04L12/933 ,  H04L12/717

Abstract: Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.

公开(公告)号：US20220199125A1

公开(公告)日：2022-06-23

申请号：US17343829

申请日：2021-06-10

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Saurabh Pijuskumar Sinha ,  Shidhartha Das ,  Mudit Bhargava ,  Rahul Mathur

IPC: G11C5/14 ,  G11C5/02

Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.

公开(公告)号：US20220130816A1

公开(公告)日：2022-04-28

申请号：US17077532

申请日：2020-10-22

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  H01L25/065 ,  H01L23/535 ,  H01L21/768 ,  H01L25/00 ,  G06F30/31

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

公开(公告)号：US11295053B2

公开(公告)日：2022-04-05

申请号：US16569482

申请日：2019-09-12

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Stephen Lewis Moore ,  Mudit Bhargava

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/327 ,  G06F111/20

Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

公开(公告)号：US10825745B1

公开(公告)日：2020-11-03

申请号：US16666816

申请日：2019-10-29

Applicant: Arm Limited

Inventor： Saurabh Pijuskumar Sinha ,  Xiaoqing Xu ,  Joel Thornton Irby ,  Mudit Bhargava

IPC: H01L21/66 ,  H01L25/18 ,  G06F30/30 ,  G06F30/333

Abstract: A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.

公开(公告)号：US20170365600A1

公开(公告)日：2017-12-21

申请号：US15188544

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Robert Campbell Aitken ,  Brian Tracy Cline ,  Gregory Munson Yeric ,  Kyungwook Chang

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/73207

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.