公开(公告)号：US11569219B2

公开(公告)日：2023-01-31

申请号：US17077532

申请日：2020-10-22

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  G06F30/31 ,  H01L21/768 ,  H01L23/535 ,  H01L25/065 ,  H01L25/00

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

公开(公告)号：US20220164513A1

公开(公告)日：2022-05-26

申请号：US17103251

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Chien-Ju Chao ,  Pranavi Chandupatla ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Xiaoqing Xu

IPC: G06F30/392 ,  H01L25/065 ,  G06F30/3947

Abstract: According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.

公开(公告)号：US20210081508A1

公开(公告)日：2021-03-18

申请号：US16569482

申请日：2019-09-12

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Stephen Lewis Moore ,  Mudit Bhargava

IPC: G06F17/50

Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

公开(公告)号：US20200279067A1

公开(公告)日：2020-09-03

申请号：US16877400

申请日：2020-05-18

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Stephen Lewis Moore

IPC: G06F30/394 ,  G06F30/392

Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.

公开(公告)号：US20200218845A1

公开(公告)日：2020-07-09

申请号：US16820471

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/522

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

公开(公告)号：US09929149B2

公开(公告)日：2018-03-27

申请号：US15188544

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Robert Campbell Aitken ,  Brian Tracy Cline ,  Gregory Munson Yeric ,  Kyungwook Chang

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/73207

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

公开(公告)号：US11899583B2

公开(公告)日：2024-02-13

申请号：US17388927

申请日：2021-07-29

Applicant: Arm Limited

Inventor： Joshua Randall ,  Alejandro Rico Carro ,  Dam Sunwoo ,  Saurabh Pijuskumar Sinha ,  Jamshed Jalal

IPC: G06F12/0811 ,  G06F12/084 ,  H04L45/42 ,  H04L49/109 ,  G06F12/0813 ,  G06F12/0893

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/0893 ,  H04L45/42 ,  H04L49/109

Abstract: Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.

公开(公告)号：US11625522B2

公开(公告)日：2023-04-11

申请号：US16861286

申请日：2020-04-29

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Kyungwook Chang ,  Brian Tracy Cline ,  Ebbin Raney Southerland, Jr.

IPC: G06F30/34 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312

Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

公开(公告)号：US11455454B2

公开(公告)日：2022-09-27

申请号：US17103251

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Chien-Ju Chao ,  Pranavi Chandupatla ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Xiaoqing Xu

IPC: G06F30/00 ,  G06F30/394 ,  G06F30/392 ,  H01L25/065 ,  G06F30/3947

Abstract: According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.

公开(公告)号：US11228316B2

公开(公告)日：2022-01-18

申请号：US16522461

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Chien-Ju Chao

IPC: G05F1/04 ,  H03K3/00 ,  H03L7/08 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12

Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.