公开(公告)号：US6020229A

公开(公告)日：2000-02-01

申请号：US873130

申请日：1997-06-11

申请人： Tomoko Yamane ,  Norihisa Arai

发明人： Tomoko Yamane ,  Norihisa Arai

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8247 ,  H01L23/522 ,  H01L27/06 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L21/4763

CPC分类号： H01L27/11526 ,  H01L27/0629 ,  H01L27/1052 ,  H01L27/11541 ,  H01L28/20

摘要： There are provided a semiconductor device and a method for manufacturing the same in which a thin film polysilicon film having a small parasitic capacitance which is required for attaining the high-speed operation and high reliability can be used as a resistance element, the process margin can be increased without increasing the number of manufacturing steps, and defects due to leakage between the resistance element and the underlying substrate can be eliminated so as to ensure the high manufacturing yield. In a semiconductor device having a conductive film formed over the surface of a semiconductor substrate with a first insulating film disposed therebetween and a metal wiring layer connected to the conductive film via a contact hole formed in a second insulating film which is formed on the conductive film, an etching stopper film having a selective etching ratio with respect to the second insulating film is formed in an area directly below the contact hole with a third insulating film disposed therebetween.

摘要翻译： 提供了一种半导体器件及其制造方法，其中可以使用具有用于获得高速操作和高可靠性所需的具有小寄生电容的薄膜多晶硅膜作为电阻元件，工艺余量可以 在不增加制造步骤的数量的情况下增加，并且可以消除由于电阻元件和下面的基板之间的泄漏引起的缺陷，从而确保高的制造成品率。 在具有导电膜的半导体器件中，在半导体衬底的表面上形成有第一绝缘膜，并且金属布线层通过形成在导电膜上的第二绝缘膜上形成的接触孔连接到导电膜上 在第二绝缘膜上具有选择性蚀刻比的蚀刻阻挡膜形成在接触孔正下方的区域，其间设置有第三绝缘膜。

公开(公告)号：US5933731A

公开(公告)日：1999-08-03

申请号：US823979

申请日：1997-03-25

申请人： Masao Tanimoto ,  Norihisa Arai

发明人： Masao Tanimoto ,  Norihisa Arai

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76202 ,  H01L21/823462

摘要： The element separation region has a section on its surface, where the first resist pattern and second resist pattern overlap with each other. The overlapping section is not etched even while removing the dummy oxide films formed in the first and second regions divided by the element separation region. Therefore, a sufficient thickness of the element separation region is kept. Further, by providing the overlapping section, the formation of sources of generating dust, namely, fine recesses and projections on the element separation region, can be prevented if an masking error occurs. Consequently, the step of removing the dust generating sources is not necessary, thereby reducing the number of manufacturing steps.

摘要翻译： 元件分离区域在其表面上具有第一抗蚀剂图案和第二抗蚀剂图案彼此重叠的部分。 即使在除去由元件分离区域分割的第一和第二区域中形成的虚拟氧化膜的情况下，也不会蚀刻重叠部分。 因此，保持元件分离区域的足够的厚度。 此外，通过提供重叠部分，如果发生掩蔽误差，则可以防止形成产生粉尘的源，即元件分离区上的细小凹凸。 因此，不需要去除除尘产生源的步骤，从而减少制造步骤的数量。

公开(公告)号：US5469397A

公开(公告)日：1995-11-21

申请号：US337209

申请日：1994-11-08

申请人： Chiaki Hoshino ,  Norihisa Arai

发明人： Chiaki Hoshino ,  Norihisa Arai

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28 ,  G11C7/02

CPC分类号： G11C16/28

摘要： The memory cells connected to the word lines in the odd-numbered rows differ from the memory cells connected to the word lines in the even-numbered rows in characteristics. A dummy cell DMC1 has the same characteristics as those of the memory cells connected to the word lines in the odd-numbered rows, and a dummy cell DMC2 has the same characteristics as those of the memory cells connected to the word lines in the even-numbered rows. Because the dummy cell DMC1 is selected together with a word line in an odd-numbered row, and the dummy cell DMC2 is selected together with a word line in an even-numbered row, a suitable reference potential can be supplied in accordance with the selected memory cell. A sense amplifier compares the potential on the bit line to which the selected memory cell is connected with the potential supplied from the selected dummy cell. Therefore, the sense amplifier can sense the potential at the selected memory cell accurately.

摘要翻译： 连接到奇数行中的字线的存储单元与连接到偶数行中的字线的存储单元的特性不同。 虚拟单元DMC1具有与连接到奇数行中的字线的存储单元相同的特性，并且虚拟单元DMC2具有与偶数行中的字线连接的存储单元的特性相同的特性， 编号行。 由于虚拟单元DMC1与奇数行中的字线一起选择，并且虚拟单元DMC2与偶数行中的字线一起选择，所以可以根据所选择的参考电位提供合适的参考电位 记忆单元 读出放大器将所选择的存储器单元所连接的位线上的电位与从所选择的虚拟单元提供的电位进行比较。 因此，读出放大器可以精确地感测所选存储单元的电位。

公开(公告)号：US5389808A

公开(公告)日：1995-02-14

申请号：US199018

申请日：1994-02-18

申请人： Norihisa Arai

发明人： Norihisa Arai

IPC分类号： H01L27/04 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/66825

摘要： In a semiconductor device, a first gate electrode and isolation layers are formed on a first gate insulation layer on a p-type silicon semiconductor substrate, and a second gate electrode is formed on the first gate electrode with a second gate insulation layer interposed therebetween. The first gate electrode is constituted by a first polycrystalline silicon layer, a second polycrystalline silicon layer and an etching stopper thin film interposed therebetween. The first gate electrode is formed by anisotropic-etching or selectively etching the second polycrystalline silicon layer, so that the etching stopper is maintained.

摘要翻译： 在半导体器件中，第一栅电极和隔离层形成在p型硅半导体衬底上的第一栅极绝缘层上，并且第二栅电极形成在第一栅电极上，第二栅极绝缘层介于它们之间。 第一栅极由介于其间的第一多晶硅层，第二多晶硅层和蚀刻停止薄膜构成。 第一栅电极通过各向异性蚀刻或选择性蚀刻第二多晶硅层形成，从而保持蚀刻停止。